A Framework for High Level Estimations of Signal Processing VLSI Implementations

[1]  Olivier Sentieys,et al.  Memory unit design for real time DSP applications , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[2]  Eric Martin,et al.  A study on discrete wavelet transform implementation for a high level synthesis tool , 1998, 9th European Signal Processing Conference (EUSIPCO 1998).

[3]  Jean-Philippe Diguet,et al.  Area/Time/Power space exploration in module selection for DSP high level synthesis , 1997 .

[4]  Olivier Sentieys,et al.  Memory module selection for high level synthesis , 1996, VLSI Signal Processing, IX.

[5]  Olivier Sentieys,et al.  Hardware module selection for real time pipeline architectures using probabilistic cost estimation , 1996, Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit.

[6]  Daniel Gajski,et al.  A memory selection algorithm for high-performance pipelines , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[7]  P. E. R. Lippens,et al.  CAD challenges in multimedia computing , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[8]  Taewhan Kim,et al.  A new approach to the multiport memory allocation problem in data path synthesis , 1995, Integr..

[9]  P. Duhamel,et al.  Implementation and performance of composite fast FIR filtering algorithms , 1995, VLSI Signal Processing, VIII.

[10]  Hugo De Man,et al.  Scheduling with register constraints for DSP architectures , 1994, Integr..

[11]  H. De Man,et al.  Dataflow-driven Memory Allocation For Multi-dimensional Signal Processing Systems , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[12]  Miodrag Potkonjak,et al.  System-level design guidance using algorithm properties , 1994, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing.

[13]  Sun-Young Hwang,et al.  Design of a pipelined datapath synthesis system for digital signal processing , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Jan M. Rabaey,et al.  Memory Estimation for High Level Synthesis , 1994, 31st Design Automation Conference.

[15]  Miodrag Potkonjak,et al.  Estimating implementation bounds for real time DSP application specific circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Minjoong Rim,et al.  Lower-bound performance estimation for the high-level synthesis scheduling problem , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  H. De Man,et al.  Exact evaluation of memory size for multi-dimensional signal processing systems , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[18]  Olivier Sentieys,et al.  GAUT: An architectural synthesis tool for dedicated signal processors , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

[19]  K. J. Ray Liu,et al.  Unified parallel lattice structures for time-recursive discrete cosine/sine/Hartley transforms , 1993, IEEE Trans. Signal Process..

[20]  Alice C. Parker,et al.  Predicting system-level area and delay for pipelined and nonpipelined designs , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Barry M. Pangrle,et al.  On the complexity of connectivity binding , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[22]  Pierre Duhamel,et al.  Short-length FIR filters and their use in fast nonrecursive filtering , 1991, IEEE Trans. Signal Process..

[23]  Donald E. Thomas,et al.  Exploiting the special structure of conflict and compatibility graphs in high-level synthesis , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[24]  Jacob Benesty,et al.  A fast exact least mean square adaptive algorithm , 1990, International Conference on Acoustics, Speech, and Signal Processing.

[25]  Peter B. Denyer,et al.  Synthesis of address generators , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[26]  Arun K. Majumdar,et al.  Allocation of multiport memories in data path synthesis , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[27]  Richard E. Blahut,et al.  Fast Algorithms for Digital Signal Processing , 1985 .

[28]  D. Patterson,et al.  Computer Architecture - A Quantitative Approach, 5th Edition , 1969 .

[29]  J. Diguet Estimation de complexite et transformations d' algorithmes de traitement du signal pour la conception de circuits vlsi , 1996 .

[30]  Keshab K. Parhi,et al.  High-level DSP synthesis using concurrent transformations, scheduling, and allocation , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[31]  Olivier Sentieys,et al.  Synthesis: From Digital Signal Processing Specifications to Layout , 1995 .

[32]  H. De Man,et al.  Verification of loop transformations for real time signal processing applications , 1994, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing.

[33]  Alok Sharma,et al.  Estimation and design algorithms for the behavioral synthesis of asics , 1992 .

[34]  Keshab K. Parhi,et al.  Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered look-ahead and decomposition , 1989, IEEE Trans. Acoust. Speech Signal Process..

[35]  M. Golumbic Algorithmic graph theory and perfect graphs , 1980 .