A scalable architecture of a structured LDPC decoder

We present a scalable decoding architecture for a certain class of structured LDPC codes. The codes are designed using a small (n, r) protograph that is replicated Z times to produce a decoding graph for a (Z/spl times/n, Z/spl times/r) code. Using this architecture, we have implemented a decoder for a (4096, 2048) LDPC code on a Xilinx Virtex-II 2000 FPGA, and achieved decoding speeds of 31 Mbps with 10 fixed iterations. The implemented message-passing algorithm uses an optimized 3-bit nonuniform quantizer that allows near floating point performance in the waterfall region, with drastically smaller hardware implementation requirements.

[1]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[2]  Robert Michael Tanner,et al.  A recursive approach to low complexity codes , 1981, IEEE Trans. Inf. Theory.

[3]  Sae-Young Chung,et al.  On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit , 2001, IEEE Communications Letters.

[4]  Evangelos Eleftheriou,et al.  Progressive edge-growth Tanner graphs , 2001, GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270).

[5]  J. Thorpe.  Low-Density Parity-Check (LDPC) Codes Constructed from Protographs , 2003 .

[6]  Tong Zhang,et al.  Design of VLSI implementation-oriented LDPC codes , 2003, 2003 IEEE 58th Vehicular Technology Conference. VTC 2003-Fall (IEEE Cat. No.03CH37484).

[7]  Samuel Dolinar,et al.  Methodologies for designing LDPC codes using protographs and circulants , 2004, International Symposium onInformation Theory, 2004. ISIT 2004. Proceedings..