An exploration of hierarchical design implementation flows

In microelectronics technology scaling is applied in order to improve the performance, energy efficiency and cost of embedded systems. As technology scales down to the Deep Sub Micron (DSM) era, wires start to consume relatively more energy than the billions of transistors on a chip. Hence, in future Systems on Chip (SoC), the energy consumption will be dominated by wires. The delay of gates and local wires decreases with scaling, but that of global wires increases due to dimension miniaturization and new parasitic effects. For this reason, global wires will define the performance of nextgeneration systems. The goal of this thesis is to create a back-end methodology which keeps the energy consumption of especially global wires low while regarding timing closure. Wire energy is mostly determined by its switching activity and capacitance. Since the switching activity of a wire is usually already optimized at the application level, a gain in its energy consumption can mainly be obtained by reducing the capacitance or rather the length of particularly highly active wires.The suggested methodology is based on hierarchical physical design. Local wires are kept short by implementing macros; the lengths of global highly active wires are minimized during floorplanning. In the course of this thesis, a fully hierarchical as well as two hybrid design flows are proposed. Distinctions from the conventional design flow are highlighted and explained. In order to verify the concepts, all aforementioned design flows were implemented with popular commercial tools and applied to two state-of-the-art systems developed at IMEC. The results, which are based on the 90nm technology node, have shown that the approach of hierarchical design combined with activity aware floorplanning can improve the energy consumption of interconnections in specific cases. However, it can also be observed that the application of the proposed design flows is not very well-suited for control-dominated processor cores. To explain these findings, conclusions of different analysis are shown and improvements are submitted.

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