A survey about testing asynchronous circuits

Even though the asynchronous design methodology is considered to be a promising solution to upcoming challenges of designing complex integrated circuits (ICs), it is not widely accepted by the industry. Besides the lack of mature design tools, a further key inhibitor of using this design style is the widespread assumption that asynchronous circuits are difficult to test due to problems with system timing during test, nondeterminism, and difficulties with applying standard test approaches such as scan. However, there is a huge variety of approaches to handle these testing issues. This paper summarizes the different available test methodologies for asynchronous and globally-asynchronous locally-synchronous (GALS) designs and addresses their strengths and weaknesses. Moreover, it gives an overview of a methodology for testing based on the use of specific test processor, developed by IHP.

[1]  Hans G. Kerkhoff,et al.  Automatic scan insertion and test generation for asynchronous circuits , 2002, Proceedings. International Test Conference.

[2]  Erik Brunvand,et al.  Testing micropipelines , 1994, Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems.

[3]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[4]  Kewal K. Saluja,et al.  Testing micropipelined asynchronous circuits , 2004, 2004 International Conferce on Test.

[5]  Steve Furber,et al.  Principles of Asynchronous Circuit Design: A Systems Perspective , 2010 .

[6]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について － , 2004 .

[7]  Rolf Kraemer,et al.  Design of a Test Processor for Asynchronous Chip Test , 2011, 2011 Asian Test Symposium.

[8]  Volker Schöber,et al.  An asynchronous scan path concept for micropipelines using the bundled data convention , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[9]  Alexandre Yakovlev,et al.  Low-Cost Online Testing of Asynchronous Handshakes , 2006, Eleventh IEEE European Test Symposium (ETS'06).

[10]  Erik Brunvand,et al.  A partial scan methodology for testing self-timed circuits , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[11]  Alian J. Martin,et al.  Testing delay-insensitive circuits , 1991 .

[12]  Shai Rotem,et al.  CA-BIST for asynchronous circuits: a case study on the RAPPID asynchronous instruction length decoder , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[13]  Wayne P. Burleson,et al.  Synchro-tokens: a deterministic GALS methodology for chip-level debug and test , 2005, IEEE Transactions on Computers.

[14]  Gaetano Borriello,et al.  Testing asynchronous circuits: A survey , 1995, Integr..

[15]  Jens Sparsø,et al.  Principles of Asynchronous Circuit Design , 2001 .

[16]  Stephen B. Furber,et al.  Scan testing of micropipelines , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[17]  Stephen B. Furber,et al.  Scan testing of asynchronous sequential circuits , 1995, Proceedings. Fifth Great Lakes Symposium on VLSI.

[18]  Eckhard Grass,et al.  BIST technique for GALS systems , 2005, 8th Euromicro Conference on Digital System Design (DSD'05).

[19]  Rolf Kraemer,et al.  On-line testing of bundled-data asynchronous handshake protocols , 2010, 2010 IEEE 16th International On-Line Testing Symposium.

[20]  Alexander Saldanha,et al.  Partial scan delay fault testing of asynchronous circuits , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).