Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices

This paper investigates the feasibility of sub-0.2 V high-speed low-power circuits with hetero-channel MOSFET and emerging Tunneling FET (TFET) devices. First, the device designs and characteristics of hetero-channel MOSFET and TFET devices are discussed and compared. Due to the significant leakage current of ultra-low VT hetero-channel MOSFET devices, assist-circuits are required for hetero-channel MOSFET-based circuits to operate at 0.2 V. Second, the delay, dynamic energy and the Standby power of hetero-channel TFET-based and MOSFET-based logic circuits including Inverter, NAND, BUS Driver, and Latch are analyzed and evaluated. The results indicate that hetero-channel TFET-based circuits with Dual Oxide (DOX) device design to reduce the Miller capacitance provide the potential to achieve high-speed low-power operation at VDD=0.2 V, while the use of assist-circuits in MOSFET-based design improves the delay and dynamic energy at the expense of increased device count, circuit area, and large Standby and sleep-mode leakage power. Finally, the impacts of temperature and process variations on TFET-based and MOSFET-based logic circuits are discussed.

[1]  Qin Zhang,et al.  Low-subthreshold-swing tunnel transistors , 2006, IEEE Electron Device Letters.

[2]  Masashi Horiguchi,et al.  Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[3]  Narayanan Vijaykrishnan,et al.  An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[4]  K. Boucart,et al.  Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric , 2007, IEEE Transactions on Electron Devices.

[5]  S. Datta,et al.  Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[6]  Byung-Gook Park,et al.  Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec , 2007, IEEE Electron Device Letters.

[7]  H. Ota,et al.  Experimental demonstration of temperature stability of Si-tunnel FET over Si-MOSFET , 2012, 2012 IEEE Silicon Nanoelectronics Workshop (SNW).

[8]  K. Boucart,et al.  Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric , 2007 .

[9]  Kiyoo Itoh,et al.  Adaptive circuits for the 0.5-V nanoscale CMOS era , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[10]  T. Suligoj,et al.  Features of electron mobility in ultrathin-body InGaAs-on-insulator MOSFETs down to body thickness of 2 nm , 2011, IEEE 2011 International SOI Conference.

[11]  S. Takagi,et al.  High mobility CMOS technologies using III-V/Ge channels on Si platform , 2012, 2012 13th International Conference on Ultimate Integration on Silicon (ULIS).

[12]  G. Ghibaudo,et al.  Localized ultra-thin GeOI: An innovative approach to germanium channel MOSFETs on bulk Si substrates , 2008, 2008 IEEE International Electron Devices Meeting.

[13]  S. Datta,et al.  Effective Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation , 2009, IEEE Transactions on Electron Devices.

[14]  Yusuf Leblebici,et al.  Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[15]  O. Faynot,et al.  GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current , 2010, IEEE Electron Device Letters.

[16]  H. Riel,et al.  InAs–Si Nanowire Heterojunction Tunnel FETs , 2012, IEEE Electron Device Letters.

[17]  Saurabh Dighe,et al.  A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.

[18]  R. Narang,et al.  Impact of Temperature Variations on the Device and Circuit Performance of Tunnel FET: A Simulation Study , 2013, IEEE Transactions on Nanotechnology.