A Low Power 10-Bit 30MSPS Pipelined A/D Converter

A low power 10-bit 30 MS/s pipelined A/D converter was designed based on 0.18 μm CMOS mixed signal technology.In this circuit,low power was achieved by optimizing values of sampling capacitors and bias current of the OTA in each stage,together with the use of dynamic comparators.Bootstrapped switches were used to reduce the nonlinearity of switches.High resolution was realized by introducing digital calibration technology.Simulation results showed that the proposed ADC had an SNDR of 59 dB and an SFDR of 71 dB at 32 MS/s sampling rate for an input signal of 16 MHz.The ADC occupies a chip area of 0.64 mm2,and it consumes only 32 mW of power.