Hierarchical extraction of critical area for shorts in very large ICs

This paper describes an algorithm for efficiently extracting critical area in large VLSI circuits. The algorithm, implemented to handle shorts between electrical nets, takes advantage of the available hierarchy in the layout description in order to speed-up computation and minimize memory usage. The developed software-CREST-was tested for a spectrum of actual IC designs and was found very efficient as compared to existing techniques.

[1]  Louis K. Scheffer,et al.  Hierarchical Analysis of IC Artwork with User Defined Abstraction Rules , 1985, DAC 1985.

[2]  C. H. Stapper,et al.  Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product , 1980, IBM J. Res. Dev..

[3]  Wojciech Maly,et al.  Yield estimation model for VLSI artwork evaluation , 1983 .

[4]  Wojciech Maly,et al.  Circuit design for a large area high-performance crossbar switch , 1991, [Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems.

[5]  A. V. Ferris-Prabhu,et al.  Modeling the critical area in yield forecasts , 1985 .

[6]  Walter S. Scott,et al.  Magic: A VLSI Layout System , 1984, 21st Design Automation Conference Proceedings.

[7]  Nils Hedenstiema.  The Halo Algorithm-An Algorithm for Hierarchical Design of Rule Checking of VLSI Circuits , 1993 .

[8]  Wojciech Maly,et al.  Computer-aided design for VLSI circuit manufacturability , 1990, Proc. IEEE.

[9]  David Marple,et al.  Tailor: a layout system based on trapezoidal corner stitching , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Andrzej J. Strojwas,et al.  The CDB/HCDB semiconductor wafer representation server , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Andrzej J. Strojwas,et al.  VLSI Yield Prediction and Estimation: A Unified Framework , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Michael Ian Shamos,et al.  Computational geometry: an introduction , 1985 .

[13]  J. Pineda de Gyvez,et al.  IC defect sensitivity for footprint-type spot defects , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Wojciech Maly,et al.  Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Charles H. Stapper,et al.  Modeling of Integrated Circuit Defect Sensitivities , 1983, IBM J. Res. Dev..

[16]  Wojciech Maly,et al.  Memory chip for 24-port global register file , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[17]  Wojciech Maly,et al.  SRAM-based extraction of defect characteristics , 1994, Proceedings of 1994 IEEE International Conference on Microelectronic Test Structures.

[18]  A. Ferris-Prabhu.  Role of defect size distribution in yield modeling , 1985, IEEE Transactions on Electron Devices.

[19]  D. M. H. Walker,et al.  VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Dinesh D. Gaitonde,et al.  Test quality and yield analysis using the DEFAM defect to fault mapper , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[21]  Thomas Waas,et al.  AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout , 1995, Proceedings of International Workshop on Defect and Fault Tolerance in VLSI.

[22]  George S. Taylor,et al.  Magic's Incremental Design-Rule Checker , 1984, 21st Design Automation Conference Proceedings.

[23]  Wojciech Maly,et al.  Cost of Silicon Viewed from VLSI Design Perspective , 1994, 31st Design Automation Conference.

[24]  M. E. Thomas,et al.  Extraction of defect size distributions in an IC layer using test structure data , 1994 .