Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators With Inductor

In this paper, a concept of chip-package-board (CPB) interactive physically unclonable function (PUF) is presented as a physical countermeasure against malicious counterfeiting at not only chip fabrication but also at package/board assembly stages. A fully CMOS compatible coupled chaos oscillator with inductive wireless interaction incorporates assembly variations into PUF identification (ID) generations without any additional process/assembly options. Chaos is essentially not a random phenomenon but a deterministic non-periodic flow which can be utilized to extract reproducible ID. The strong parametric sensitivity of the chaos guarantees ID variety and unclonability over unpredictable process/assembly variations. An undesirable disturbance due to dynamic parametric fluctuations can be removed by phase-locked loop (PLL)-based replica feedback compensation together with mixed-signal post-processing for stable ID reproduction. The proposed CPB interactive PUF is silicon prototyped in 0.18- $\mu \text{m}$ CMOS for the proof of the concept. Eight samples of a compact 3150 $\mu \text{m}^{2}$ PUF successfully reproduce 512-bit unique IDs with <2.5% bit error rate (BER) before and after assembly. This for the first time demonstrates a potential capability of PUF ID traceability extended through CPB process/assembly stages for an advanced secure supply chain.

[1]  Yongki Lee,et al.  8.7 Physically unclonable function for secure key generation with a key error rate of 2E-38 in 45nm smart-card chips , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[2]  Patrick Schaumont,et al.  A large scale characterization of RO-PUF , 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[3]  Chih-Min Wang,et al.  A PUF scheme using competing oxide rupture with bit error rate approaching zero , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[4]  Marten van Dijk,et al.  A technique to build a secret key in integrated circuits for identification and authentication applications , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[5]  Himanshu Kaul,et al.  16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[6]  Jorge Guajardo,et al.  FPGA Intrinsic PUFs and Their Use for IP Protection , 2007, CHES.

[7]  Mark Mohammad Tehranipoor,et al.  Secure Split-Test for preventing IC piracy by untrusted foundry and assembly , 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

[8]  John Villasenor,et al.  Chop shop electronics , 2013, IEEE Spectrum.

[9]  R. Rovatti,et al.  A Fast Chaos-based True Random Number Generator for Cryptographic Applications , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

[10]  Stephen A. Benton,et al.  Physical one-way functions , 2001 .

[11]  Michael A. Lieberman,et al.  Secure random number generation using chaotic circuits , 1989, IEEE Military Communications Conference, 'Bridging the Gap. Interoperability, Survivability, Security'.

[13]  Ahmad-Reza Sadeghi,et al.  Efficient Helper Data Key Extractor on FPGAs , 2008, CHES.

[14]  G. Edward Suh,et al.  Physical Unclonable Functions for Device Authentication and Secret Key Generation , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[15]  Blaauw David,et al.  8.3 A 553F2 2-transistor amplifier-based Physically Unclonable Function (PUF) with 1.67% native instability , 2017 .

[16]  Naoya Tate,et al.  Nano-artifact metrics based on random collapse of resist , 2014, Scientific Reports.

[17]  Ying Su,et al.  A 1.6pJ/bit 96% Stable Chip-ID Generating Circuit using Process Variations , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[18]  Masanori Takahashi,et al.  Chaos, deterministic non-periodic flow, for chip-package-board interactive PUF , 2017, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC).

[19]  Massimo Alioto,et al.  14.3 15fJ/b static physically unclonable functions for secure chip identification with <2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[20]  W. R. Daasch,et al.  IC identification circuit using device mismatch , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[21]  Yoonmyung Lee,et al.  A 445F2 leakage-based physically unclonable Function with Lossless Stabilization Through Remapping for IoT Security , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[22]  Srinivas Devadas,et al.  Silicon physical random functions , 2002, CCS '02.

[23]  E. Lorenz Deterministic nonperiodic flow , 1963 .

[24]  R. Rovatti,et al.  Embeddable ADC-based true random number generator for cryptographic applications exploiting nonlinear signal processing and chaos , 2005 .

[25]  Lawrence T. Pileggi,et al.  Building trusted ICs using split fabrication , 2014, 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[26]  M. Shinriki,et al.  Multimode oscillations in a modified Van Der Pol oscillator containing a positive nonlinear conductance , 1981, Proceedings of the IEEE.

[27]  David Blaauw,et al.  14.2 A physically unclonable function with BER <10−8 for robust chip authentication using oscillator collapse in 40nm CMOS , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.