Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation

This paper proposes a theory of transistor short faults and their detection in logic test environment. The transistor short models were defined, and the characteristics of equivalent faults and redundant faults were revealed. Also presented were a stuck-at fault simulation method and a test generation method that uses only the gate-level description of the circuits while dealing with transistor short faults. Experimental results for ISCAS benchmark circuits were presented to demonstrate the effectiveness of the methodology proposed in this paper