Partial reconfiguration of a peripheral in an FPGA-based SoC to analyse performance-area behaviour

Systems on Chip (SoC) are present in a wide range of applications. This diversity in addition with the quantity of critical variables involved in their design process becomes it as a great challenging topic. FPGAs have consolidated as a preferred device to develop and prototype SoCs, and consequently Partial Reconfiguration (PR) has gained importance in this approach. Through PR it is possible to have a section of the FPGA operating, while other section is disabled and partially reconfigured to provide new functionality. In this way hardware resources can be time-multiplexed and therefore it is possible to reduce size, cost and power. In this case we focus on the implementation of a SoC, in an FPGA-based board, with one of its peripherals being a reconfigurable partition (RP). Inside this RP different hardware modules defined as reconfigurable modules (RM) can be configured. Thus, the system is suitable to have different hardware configurations depending on the application needs and FPGA limitations, while the rest of the system continues working. To this end a MicroBlaze soft-core processor is used in the system design and a Virtex-5 FPGA board is utilized to its implementations. A remote sensing application is used to explore the capabilities of this approach. Identifying the section(s) of the application suitable of being time-shared it is possible to define the RMs to place inside the RP. Different configurations were carried out and measurements of area were taken. Preliminary results of the performance-area utilisation are presented to validate the improvement in flexibility and resource usage.