On MOS admittance modeling to study border trap capture/emission and its effect on electrical behavior of high-k/III-V MOS devices

Graphical abstractDisplay Omitted We developed an admittance model to study border traps in III-V MOS devices.Multi-phonon emission model is used for the capture/emission of carriers by traps.Our model can simulate the temperature dependence of C-V frequency dispersion.Effect of decrease in oxide thickness on frequency dispersion was simulated.Increase in dispersion with lower EOT due to enhanced oxide field and band bending. In this paper, we present results of a study on border trap capture/emission (C/E) process and its effect on small signal admittance of III-V devices. A MOS admittance model using a non-radiative multi-phonon phenomenon as the basis of the border trap capture/emission process is developed and utilized to investigate the effect of parameters like temperature, gate voltage, oxide thickness and trap distribution on capture/emission process. The simulation results are found to match closely with experimentally observed temperature, voltage and dielectric thickness dependencies in experimental admittance data.

[1]  Xiuling Li,et al.  A Distributive-Transconductance Model for Border Traps in III–V/High-k MOS Capacitors , 2013, IEEE Electron Device Letters.

[2]  Yuan Taur,et al.  Determination of energy and spatial distribution of oxide border traps in In0.53Ga0.47As MOS capacitors from capacitance-voltage characteristics measured at various temperatures , 2014, Microelectron. Reliab..

[3]  T. L. Tewksbury,et al.  Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFETs , 1993 .

[4]  Cor Claeys,et al.  Border Traps in Ge/III–V Channel Devices: Analysis and Reliability Aspects , 2013, IEEE Transactions on Device and Materials Reliability.

[5]  Y. Taur,et al.  Effects of oxide thickness and temperature on dispersions in InGaAs MOS C-V characteristics , 2014 .

[6]  E. Lind,et al.  A High-Frequency Transconductance Method for Characterization of High- $\kappa$ Border Traps in III-V MOSFETs , 2013, IEEE Transactions on Electron Devices.

[7]  N. Taoka,et al.  Impact of Fermi Level Pinning Due to Interface Traps Inside the Conduction Band on the Inversion-Layer Mobility in $\hbox{In}_{x}\hbox{Ga}_{1 - x}\hbox{As}$ Metal–Oxide–Semiconductor Field Effect Transistors , 2013, IEEE transactions on device and materials reliability.

[8]  D. Lang,et al.  Nonradiative capture and recombination by multiphonon emission in GaAs and GaP , 1977 .

[9]  T. Grasser,et al.  Time-dependent defect spectroscopy for characterization of border traps in metal-oxide-semiconductor transistors , 2010 .

[10]  M. Rodwell,et al.  A Distributed Bulk-Oxide Trap Model for $\hbox{Al}_{2} \hbox{O}_{3}$ InGaAs MOS Devices , 2012, IEEE Transactions on Electron Devices.

[11]  F. Heiman,et al.  The effects of oxide traps on the MOS capacitance , 1965 .