A 118.4 GB/s Multi-Casting Network-on-Chip With Hierarchical Star-Ring Combined Topology for Real-Time Object Recognition
暂无分享,去创建一个
Hoi-Jun Yoo | Joo-Young Kim | Seungjin Lee | Minsu Kim | Junyoung Park | Jinwook Oh | Joo-Young Kim | Minsu Kim | Seungjin Lee | Jinwook Oh | H. Yoo | Junyoung Park
[1] J.N. Seizovic,et al. Pipeline synchronization , 1994, Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems.
[2] Lionel M. Ni,et al. Multi-address Encoding for Multicast , 1994, PCRCW.
[3] Bruce S. Davie,et al. Computer Networks: A Systems Approach , 1996 .
[4] W. Dally,et al. Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[5] Jean Ponce,et al. Computer Vision: A Modern Approach , 2002 .
[6] Luca Benini,et al. Networks on Chips : A New SoC Paradigm , 2022 .
[7] Hoi-Jun Yoo,et al. An 800MHz star-connected on-chip network for application to systems on a chip , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
[8] Hoi-Jun Yoo,et al. A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[9] Frank Ghenassia,et al. Transaction Level Modeling with SystemC , 2005 .
[10] Daniela Dragomirescu,et al. Object Recognition System-on-Chip Using the Support Vector Machines , 2005, EURASIP J. Adv. Signal Process..
[11] Hoi-Jun Yoo,et al. Low-power network-on-chip for high-performance SoC design , 2006, IEEE Trans. Very Large Scale Integr. Syst..
[12] Donghyun Kim,et al. An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory , 2007, 2007 IEEE Custom Integrated Circuits Conference.
[13] Hoi-Jun Yoo,et al. Implementation of Memory-Centric NoC for 81.6 GOPS object recognition processor , 2007, 2007 IEEE Asian Solid-State Circuits Conference.
[14] Saurabh Dighe,et al. An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[15] Timothy Mark Pinkston,et al. Characterizing the Cell EIB On-Chip Network , 2007, IEEE Micro.
[16] David Clark,et al. The Morgan Kaufmann Series in Networking , 2008 .
[17] Donghyun Kim,et al. A 125GOPS 583mW Network-on-Chip Based Parallel Processor with Bio-inspired Visual-Attention Engine , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[18] Hoi-Jun Yoo,et al. Low-power NoC for high-performance SoC design , 2008 .
[19] Joo-Young Kim,et al. A 76.8 GB/s 46 mW low-latency network-on-chip for real-time object recognition processor , 2008, 2008 IEEE Asian Solid-State Circuits Conference.
[20] David Wentzlaff,et al. Processor: A 64-Core SoC with Mesh Interconnect , 2010 .
[21] Radu Marculescu,et al. Communication-Aware Face Detection Using Noc Architecture , 2008, ICVS.
[22] Hoi-Jun Yoo,et al. Real-Time Object Recognition with Neuro-Fuzzy Controlled Workload-Aware Task Pipelining , 2009, IEEE Micro.
[23] Joo-Young Kim,et al. A 125 GOPS 583 mW Network-on-Chip Based Parallel Processor With Bio-Inspired Visual Attention Engine , 2009, IEEE Journal of Solid-State Circuits.
[24] Hoi-Jun Yoo,et al. A 201.4 GOPS 496 mW Real-Time Multi-Object Recognition Processor With Bio-Inspired Neural Perception Engine , 2009, IEEE Journal of Solid-State Circuits.
[25] Frank Ghenassia. Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems , 2010 .
[26] Matthijs C. Dorst. Distinctive Image Features from Scale-Invariant Keypoints , 2011 .