论文信息 - Simultaneous switching noise analysis and low bouncing buffer design [CMOS ICs]

Simultaneous switching noise analysis and low bouncing buffer design [CMOS ICs]

An accurate equation to estimate Simultaneous Switching Noise (SSN) in CMOS integrated circuits including the carrier velocity saturation effects of the short-channel MOSFET is proposed. Simulation results show that the proposed close-form equation estimates the SSN precisely and the error is below 5% as compared with HSPICE simulation results. Design procedures of low bouncing tapered buffer that take SSN into consideration are also proposed. Finally, several output buffer design examples are implemented to verify the low bouncing buffer design.

Wei-Chung Cheng | Shyh-Jye Jou | Yu-Tao Lin

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