Compression/scan co-design for reducing test data volume, scan-in power dissipation and test application time

Testing chips is very critical to guarantee chips are fault-free before they are integrated in a system, so as to increase the reliability of the system. Although full-scan is a widely adopted design-for-test technique for LSI design and testing, the need for reducing the test data volume, scan-in power dissipation and test application time (VPT) of the full-scan designed chip is imperative. Based on the analysis of the characteristics of the variable-to-fixed run-length coding technique and the random access scan architecture, this paper presents a novel design scheme tackling all VPT issues simultaneously. Experimental results on ISCAS'89 benchmarks have shown on average 51.2%, 99.5%, 99.3% and 85.5% reduction in test data volume, average scan-in power dissipation, peak scan-in power dissipation and test application time, respectively.

[1]  Nur A. Touba,et al.  Virtual scan chains: a means for reducing scan length in cores , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[2]  Krishnendu Chakrabarty,et al.  Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[3]  Ozgur Sinanoglu,et al.  A novel scan architecture for power-efficient, rapid test , 2002, ICCAD 2002.

[4]  Jia-Guang Sun,et al.  A cost-effective scan architecture for scan testing with non-scan test power and test application cost , 2003, DAC '03.

[5]  Patrick Girard.  Survey of low-power testing of VLSI circuits , 2002, IEEE Design & Test of Computers.

[6]  A.H. El-Maleh,et al.  Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression , 2002, 9th International Conference on Electronics, Circuits and Systems.

[7]  Janak H. Patel,et al.  Reducing test application time for full scan embedded cores , 1999, Digest of Papers. Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing (Cat. No.99CB36352).

[8]  P. T. Gonciari,et al.  Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[9]  Nur A. Touba,et al.  Static compaction techniques to control scan vector power dissipation , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[10]  E.J. Marinissen,et al.  Scan chain design for test time reduction in core-based ICs , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[11]  Dong Hyun Baik,et al.  Random access scan: a solution to test power, test data volume and test time , 2004, 17th International Conference on VLSI Design. Proceedings..

[12]  Alex Orailoglu,et al.  Circularscan: a scan architecture for test cost reduction , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[13]  Wenjing Rao,et al.  Test application time and volume compression through seed overlapping , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[14]  Krishnendu Chakrabarty,et al.  System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Janak H. Patel,et al.  Test set compaction algorithms for combinational circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[16]  Nur A. Touba,et al.  Scan vector compression/decompression using statistical coding , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[17]  Hitoshi Kubota,et al.  Hard mask fabrication for magnetic random access memory elements using focused ion beam assisted selective chemical vapor deposition , 2003 .

[18]  Krishnendu Chakrabarty,et al.  A unified approach to reduce SOC test data volume, scan power and testing time , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  H. Ando,et al.  Testing VLSI with Random Access Scan , 1980 .

[20]  Alex Orailoglu,et al.  Test volume and application time reduction through scan chain concealment , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[21]  Krishnendu Chakrabarty,et al.  Test Resource Partitioning for System-on-a-Chip , 2002, Frontiers in electronic testing.

[22]  Kohei Miyase,et al.  Optimal scan tree construction with test vector modification for test compression , 2003, 2003 Test Symposium.

[23]  Nur A. Touba,et al.  Test vector decompression via cyclical scan chains and its application to testing core-based designs , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).