A 0.008mm2 2.4GHz type-I sub-sampling ring-oscillator-based phase-locked loop with a −239.7dB FoM and −64dBc reference spurs
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[1] B. Nauta,et al. A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$ , 2009, IEEE Journal of Solid-State Circuits.
[2] Behzad Razavi,et al. 25.7 A 2.4GHz 4mW inductorless RF synthesizer , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.
[3] Pavan Kumar Hanumolu,et al. 19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).
[4] Harish Krishnaswamy,et al. 19.4 A 0.0049mm2 2.3GHz sub-sampling ring-oscillator PLL with time-based loop filter achieving −236.2dB jitter-FOM , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).