A 0.008mm2 2.4GHz type-I sub-sampling ring-oscillator-based phase-locked loop with a −239.7dB FoM and −64dBc reference spurs

A ring-oscillator (RO) based PLL is presented combining a type-I architecture and a sub-sampling phase detector (SSPD). It achieves low jitter thanks to the wide-bandwidth type-I loop and low reference spurs thanks to the SSPD with its sample-and-hold function and high gain. The integrating filter capacitor is avoided, resulting in very low area. The RO PLL prototype in 65nm CMOS occupies 0.008mm2, has a loop bandwidth of 15MHz and tunes from 2 to 3.2GHz. It consumes 6.1mW at 2.4GHz with a phase noise of −122.6dBc/Hz at 1MHz offset. The measured reference spurs, RMSjitter and FoMjitter are −64.2dBc, 422fs and −239.7dB.

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