Statistical Methods Applied to CMOS Reliability Analysis -A Survey

The design of integrated circuits (ICs) and systems in sub-90nm CMOS technology is very challenging~\cite{ITRS}. The scaling down of technology not only caused an unbalanced relationship between supply voltage and transistor threshold voltage ($V_{th}$), but also induced ageing effects and variability problems. In semiconductor manufacturing, systematic and random variations exist during different fabrication steps. Moreover, once ICs are fully functional, both ageing and variability degrade ICs performance and lead to uncertainty performance distribution. In this paper, we analysis process variations based on BSIM4 transistor model.