A power planning model for implantable stimulators

This paper presents a new analytical, empirical and behavioral modular model developed for accurate evaluation of power dissipation in power conversion chains (PCC) dedicated to power up an electronic implantable device. The model is suitable for power estimation/planning in early design stages, to determine the contribution of each circuit module on the total power consumption and to estimate the input and output voltages of these modules. It is based on average power consumption model and is coded in Verilog-A. The model is verified and the results were found to be in good agreement with state-of-the-art designs for bioelectronics devices. It is flexible and robust to changes in architecture and design parameters and provides accurate and valid results in a fraction of second for a large variety of parameter values. The ease of implementing desired modules and architectures makes the model more advantageous

[1]  Prashant Goteti,et al.  Hierarchy based statistical fault simulation of mixed-signal ICs , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[2]  Thomas F. Wenisch,et al.  SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling , 2003, ISCA '03.

[3]  Massoud Pedram,et al.  Power minimization in IC design: principles and applications , 1996, TODE.

[4]  Michel Declercq,et al.  A high-efficiency CMOS voltage doubler , 1998, IEEE J. Solid State Circuits.

[5]  Mohamad Sawan,et al.  A cortical stimulator with monitoring capabilities using a novel 1 Mbps ASK data link , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[6]  A.M. Davis,et al.  Microelectronic circuits , 1983, Proceedings of the IEEE.

[7]  B. Z. Cybyk,et al.  Direct Simulation Monte Carlo: Recent Advances and Applications , 1998 .

[8]  A. Sedra.  Microelectronic circuits , 1982 .