Algorithms and architecture for multiprocessor-based circuit simulation

Accurate electrical simulation is critical to the design of high-performance integrated circuits. Logic simulators can verify function and give first-order timing information. Switch-level simulators are more effective at dealing with charge-sharing than standard logic simulators, but cannot provide accurate timing information or discover DC problems. Delay estimation techniques and cell-level simulation can be useful in constrained design methods, but must be tuned for each application, and circuit simulation must still be used to generate the cell models. None of these methods has the guaranteed accuracy that many circuit designers desire, and none can provide detailed waveform information. Detailed electrical-level simulation can predict circuit performance if devices and parasitics are modeled accurately. However, the computational requirements of conventional circuit simulators make it impractical to simulate current large circuits. In this dissertation, the implementation of Iterated Timing Analysis (ITA), a relaxation-based technique for accurate circuit simulation, on a special-purpose multiprocessor is presented. The ITA method is an SOR-Newton, relaxation-based method which uses event-driven analysis and selective trace to exploit the temporal sparsity of the electrical network. Because event-driven selective trace techniques are employed, this algorithm lends itself to implementation on a data-driven computer. Initial results indicate that data-driven multiprocessors, working with a conventional host, can provide performance improvement for electrical circuit simulation limited only by the size and structure of the circuit under analysis. This particular class of machines also seems well-suited to other network-graph-based, event-driven algorithms, such as fault simulation and many non-electrical problems.