Errata on "Measuring Experimental Error in Microprocessor Simulation"

This short paper serves to correct the errors contained in the paper entitled "Measuring Experimental Error in Microprocessor Simulation," presented at the 2001 International Symposium on Computer Architecture (ISCA-28) [2]. That paper contained a study of a validated microarchitectural simulator called sim-alpha, and included a case study that compared results obtained from a configuration of sim-alpha to those reported by Cruz et al. [1]. The comparison showed a disparity in the results between the two studies, which was invalid due to an error in the way the operand bypass network of sim-alpha was modified.In this paper, we present a revised comparison that models the bypass network in sim-alpha consistently with the work of Cruz et al. (henceforth called the reference study). After explaining the bypassing issues in detail, we show that the new comparison between the revised results and the reference study shows similar trends, thus validating the accuracy of the reference study.In addition, we (the authors of the sim-alpha study) would like to state explicitly that we regret any professional harm caused to the authors of the reference study (Cruz, González, Valero, and Topham). The original intent was to show that different simulators modeling similar targets could cause different conclusions to be drawn, thus emphasizing the need for consistency across simulators and research efforts. Since the comparison with the reference study was made with a (modified) validated simulator, and the two sets of results showed a different trend (because of the error in modeling the bypass), it is natural to infer that the reference study was incorrect. We thoughtlessly published the comparison without contacting the authors of the reference study beforehand. We apologize to them both for implying an error in their (correct) methodology and for the discourteous way in which it was presented.