Implementation of an FPGA-Based IP Core for High-Efficiency Inner-Product Computation

An IP core based-on FPGA for high-efficiency inner-product operation is implemented,in which a distributed arithmetic algorithm was introduced to compute inner-product. The required amount of ROM used for look-up-table is decreased significantly by using two memory reduction techniques,thus saving the hardware resources. Verilog HDL for the IP core is described,and the functional simulation and synthesis are carried out under Xilinx ISE4.1.