A ring oscillator based variation test chip

[1]  D. Boning,et al.  Technology scaling impact of variation on clock skew and interconnect delay , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[2]  Chenming Hu,et al.  Intra-field gate CD variability and its impact on circuit performance , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[3]  S. Nassif,et al.  Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performance , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[4]  Duane S. Boning,et al.  Simulating the impact of poly-CD wafer-level and die-level variation on circuit performance , 1997, 1997 2nd International Workshop on Statistical Metrology.

[5]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[6]  Anantha Chandrakasan,et al.  Models of Process Variations in Device and Interconnect , 2001 .

[7]  Sani R. Nassif,et al.  Modeling and forecasting of manufacturing variations , 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

[8]  Costas J. Spanos,et al.  Study of circuit sensitivity to interconnect variation , 1997, 1997 2nd International Workshop on Statistical Metrology.

[9]  Vikas Mehrotra,et al.  Modeling the effects of systematic process variation of circuit performance , 2001 .

[10]  Karen M. González-Valentín Extraction of variation sources due to layout practices , 2002 .

[11]  Ellie Quigley Perl by Example , 1996 .