Implementation of efficient parallel discrete cosine transform using stochastic logic

This paper provides a new scheme for the VLSI implementation of a parallel Discrete Cosine Transform (DCT) using stochastic logic. Stochastic computation is a number representation, which can carry out complex computations with very low hardware cost. However, the delay of data output is proportional to the length of serial sequence. We provide a new area-saving parallel DCT design to improve the system throughput by using our proposed stochastic OR-adder and OR-AND-adder. Results show the proposed parallel stochastic DCT can meet the requirement of image processing while maintaining a ± 5% performance difference compared to the traditional DCT implementation. Our synthesized chip design using the TSMC CMOS 130nm technology also shows that the proposed parallel stochastic DCT is at least 10 times more efficient in area and delay than that of the traditional DCT and the serial stochastic DCT.

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