Arithmetic unit design using 180nm TSV-based 3D stacking technology

We describe the design of two three dimensional arithmetic units (a 3D adder and a 3D multiplier) that are implemented using through-silicon-via 3D stacking technology. Compared to their 2D counterparts, our 3D adder incurs 10.6–34.3% less delay and 11.0–46.1% less energy when the width increases from 12-bit to 72-bit; the 32×32 3D multiplier incurs 14.4% less delay and 6.8% less energy, according to the post place and route results. The prototype chip including the implementations of a 3D adder, a 3D multiplier, and simple test interface has been delivered for fabrication in MIT Lincoln Laboratory, using their 3-tier SOI based 3D technology.

[1]  Gabriel H. Loh,et al.  Implementing register files for high-performance microprocessors in a die-stacked (3D) technology , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[2]  Gabriel H. Loh,et al.  Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[3]  C. Nicopoulos,et al.  Design and Management of 3D Chip Multiprocessors Using Network-in-Memory , 2006, ISCA 2006.

[4]  Mircea R. Stan,et al.  A unified design space for regular parallel prefix adders , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[5]  S StoneHarold,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973 .

[6]  Narayanan Vijaykrishnan,et al.  Architecting Microprocessor Components in 3D Design Space , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[7]  Narayanan Vijaykrishnan,et al.  Design Space Exploration for 3-D Cache , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  P. H. Ang,et al.  Generation of high speed CMOS multiplier-accumulators , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[9]  M.D. Ercegovac,et al.  Effect of wire delay on the design of prefix adders in deep-submicron technology , 2000, Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154).

[10]  Hao Hua.  Design and Verification Methodology for Complex Three-Dimensional Digital Integrated Circuit , 2007 .

[11]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.