MARTE vs. AADL for Discrete-Event and Discrete-Time Domains
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[1] Tim Weilkiens,et al. Systems engineering with SysML / UML - modeling, analysis, design , 2007 .
[2] Robert de Simone,et al. Dealing with AADL End-to-End Flow Latency with UML MARTE , 2008, 13th IEEE International Conference on Engineering of Complex Computer Systems (iceccs 2008).
[3] Alain Plantec,et al. AADL modeling and analysis of hierarchical schedulers , 2007, SIGAda '07.
[4] Stephen A. Edwards,et al. The synchronous languages 12 years later , 2003, Proc. IEEE.
[5] Edward A. Lee,et al. A framework for comparing models of computation , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] Robert de Simone,et al. Modeling AADL Data Communications with UML MARTE , 2008 .
[7] Robert de Simone,et al. Modeling time(s) , 2007, MODELS'07.
[8] Frédéric Mallet,et al. Clock Constraints in UML/MARTE CCSL , 2008 .
[9] Donal Heffernan,et al. TTCAN: a new time-triggered controller area network , 2002, Microprocess. Microsystems.
[10] Eugenio Villar. Embedded systems specification and design languages : selected contributions from FDL'07 , 2008 .
[11] Jörgen Hansson,et al. Flow Latency Analysis with the Architecture Analysis and Design Language (AADL) , 2007 .
[12] Sébastien Gérard,et al. MARTE: Also an UML Profile for Modeling AADL Applications , 2007, 12th IEEE International Conference on Engineering Complex Computer Systems (ICECCS 2007).
[13] Frédéric Mallet. Clock constraint specification language: specifying clock constraints with UML/MARTE , 2008, Innovations in Systems and Software Engineering.