Design and Analysis of Static Random Access Memory by Schmitt Trigger Topology for Low Voltage Applications

Aggressive scaling of transistor dimensions with each technology generation has resulted an increased integration density and improved device performance at the expense of increased leakage current. The Supply voltage scaling is an effective way of reducing dynamic as well as leakage power consumption. However the sensitivity of the circuit parameters increases with reduction of the supply voltage. SRAM bitcells utilizing minimum sized transistors are susceptible to various random process variations. The Schmitt Trigger based operation gives better readconstancy as well as superior write-ability compared to the standard bitcell configurations. The proposed Schmitt Trigger based bitcells integrate a built-in feedback mechanism make the process with high tolerance. In this paper an obsolete design of a differential sensing Static Random Access Memory (SRAM) bit cells for ultralow-power and ultralow-area Schmitt trigger operation is introduced. The ST bit cells incorporate a built-in feedback mechanism, provided by separate control signal if the feedback is given by the internal nodes, achieving process variation tolerance that must be used for future nano-scaled technology nodes. In this we proposed 32nm technology for designing 10T SRAM cell using Microwind.Total power about 30% is reduced due to 32 nm technology as compared to 65 nm technlology.

[1]  H. Yamauchi,et al.  A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses , 2008, IEEE Journal of Solid-State Circuits.

[2]  A.P. Chandrakasan,et al.  Static noise margin variation for sub-threshold SRAM in 65-nm CMOS , 2006, IEEE Journal of Solid-State Circuits.

[3]  Dhireesha Kudithipudi,et al.  Variation tolerant 9T SRAM cell design , 2010, GLSVLSI '10.

[4]  Anastacia B. Alvarez,et al.  Static Noise Margin of 6T SRAM Cell in 90-nm CMOS , 2011, 2011 UkSim 13th International Conference on Computer Modelling and Simulation.

[5]  Zhiyu Liu,et al.  High Read Stability and Low Leakage Cache Memory Cell , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[6]  Rajiv V. Joshi,et al.  A Disturb Decoupled Column Select 8T SRAM Cell , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[7]  A. Chandrakasan,et al.  Analyzing static noise margin for sub-threshold SRAM in 65nm CMOS , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

[8]  Masahiro Nomura,et al.  A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications , 2006, IEEE Journal of Solid-State Circuits.

[9]  A. Chandrakasan.  8.4 a 65nm 8t Sub-v T Sram Employing Sense-amplifier Redundancy , 2007 .

[10]  Magdy A. Bayoumi,et al.  Novel 7T sram cell for low power cache design , 2005, Proceedings 2005 IEEE International SOC Conference.

[11]  W. Huott,et al.  6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM , 2007, 2007 IEEE Symposium on VLSI Circuits.

[12]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[13]  H. Fujiwara,et al.  An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment , 2007, 2007 IEEE Symposium on VLSI Circuits.

[14]  K. Takeda,et al.  A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[15]  Anna W. Topol,et al.  Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[16]  W. Dehaene,et al.  Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies , 2006, IEEE Journal of Solid-State Circuits.