MOSFET scalability limits and "new frontier" devices

Silicon-based MOSFETs are scalable to gate-lengths around 10 nm but will fall well short of commensurate performance enhancement. High mobility materials and device structures that eliminate the use of doping for electrostatic control will have to be incorporated in future CMOS technologies, along with very low contact resistance processes. New frontier FETs incorporating entirely new transport principles show promise but are still far from practical implementation.

[1]  D. Antoniadis,et al.  Carrier mobilities and process stability of strained Si n- and p-MOSFETs on SiGe virtual substrates , 2001 .

[2]  D. Antoniadis,et al.  Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress , 2001, IEEE Electron Device Letters.

[3]  Dimitri A. Antoniadis,et al.  Strained Ge channel p-type metal–oxide–semiconductor field-effect transistors grown on Si1−xGex/Si virtual substrates , 2001 .

[4]  Zhenan Bao,et al.  Self-assembled monolayer organic field-effect transistors , 2001, Nature.

[5]  C. Dekker,et al.  Logic Circuits with Carbon Nanotube Transistors , 2001, Science.

[6]  D. Antoniadis,et al.  On experimental determination of carrier velocity in deeply scaled NMOS: how close to the thermal limit? , 2001, IEEE Electron Device Letters.

[7]  G. Dewey,et al.  30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[8]  C. Hu,et al.  Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[9]  K. Rim,et al.  Fabrication and analysis of deep submicron strained-Si n-MOSFET's , 2000 .

[10]  N. Sugiyama,et al.  Electron and hole mobility enhancement in strained-Si MOSFET's on SiGe-on-insulator substrates fabricated by SIMOX technology , 2000, IEEE Electron Device Letters.

[11]  S. Laux,et al.  Performance degradation of small silicon devices caused by long-range Coulomb interactions , 2000 .

[12]  Mark S. Lundstrom Elementary scattering theory of the Si MOSFET , 1997, IEEE Electron Device Letters.

[13]  L. T. Su,et al.  A study of deep-submicron MOSFET scaling based on experiment and simulation , 1995 .

[14]  E. Sangiorgi,et al.  Silicon MOS transconductance scaling into the overshoot regime , 1993, IEEE Electron Device Letters.

[15]  T. Jackson,et al.  Gate-Self-Aligned N-Channel and P-Channel Germanium Mosfets , 1991, [1991] 49th Annual Device Research Conference Digest.

[16]  D. Kern,et al.  High transconductance and velocity overshoot in NMOS devices at the 0.1- mu m gate-length level , 1988, IEEE Electron Device Letters.

[17]  H.I. Smith,et al.  Electron velocity overshoot at room and liquid nitrogen temperatures in silicon inversion layers , 1988, IEEE Electron Device Letters.