An FPGA architecture with enhanced datapath functionality

Although FPGAs are a cost-efficient alternative for both ASICs and general purpose processors, they still result in designs which are more than an order of magnitude more costly and slower than their equivalents implemented in dedicated logic. This efficiency gap makes FPGAs less suitable for high-volume cost-sensitive applications (e.g. embedded systems).We show that the intrinsic cost of traditional general-purpose FPGAs can be reduced if they are designed to target an application domain or a class of applications only. We propose a method of the application-domain characterization and apply it to characterize DSP. A novel FPGA logic block architecture derived based on such an analysis, and which exploits properties of target applications, is presented. Its key feature is the 'mixed-level granularity' being a trade-off between fine and coarse granularity required for the implementation of datapath and random logic functions, respectively. This leads to a factor of four improvement in the LUT memory size compared to commercial FPGAs, and, assuming a standard-cell implementation, a 1.6-2.8 lower datapath mapping cost. A modified mixed-grain architecture with the ALU-like functionality reduces the LUT memory size by a factor of 16 compared to commercial FPGAs, and mapped onto standard cells has a 1.9-3.3 times higher datapath mapping efficiency. For these reasons, the proposed FPGA architectures may be an interesting alternative to the traditional general-purpose FPGA devices, especially if characteristics of a target application domain are known a priority.

[1]  Jonathan Rose,et al.  The effect of logic block complexity on area of programmable gate arrays , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[2]  Poras T. Balsara,et al.  An architecture for a DSP field-programmable gate array , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Reto Zimmermann Computer Arithmetic: Principles, Architectures, and VLSI Design , 1999 .

[4]  Steven F. Quigley,et al.  A Novel Field Programmable Gat Array Architecture for High Speed Arithmetic Processing , 1998, FPL.

[5]  Low Energy Field-Programmable Gate Array , .

[6]  RoseJonathan,et al.  The design of an SRAM-based field-programmable gate arraypart I , 1999 .

[7]  Jan M. Rabaey,et al.  Digital Integrated Circuits , 2003 .

[8]  Jef L. van Meerbergen,et al.  Embedded Reconfigurable Logic Core for DSP Applications , 2002, FPL.

[9]  André DeHon,et al.  Reconfigurable architectures for general-purpose computing , 1996 .

[10]  P. Chow,et al.  The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Scott Hauck,et al.  Totem: Custom Reconfigurable Array Generation , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[12]  Jonathan Rose,et al.  Advantages of heterogeneous logic block architecture for FPGAs , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[13]  Pierre Marchal,et al.  Field-programmable gate arrays , 1999, CACM.

[14]  Stephen D. Brown,et al.  Computational field programmable architecture , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[15]  I. Xilinx,et al.  Virtex? 2. 5v field programmable gate arrays , 2000 .

[16]  K. Leijten-Nowak,et al.  Applying the adder inverting property in the design of cost-efficient reconfigurable logic , 2001, Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257).

[17]  Jean Vuillemin,et al.  A reconfigurable arithmetic array for multimedia applications , 1999, FPGA '99.

[18]  Don Cherepacha,et al.  DP-FPGA: An FPGA Architecture Optimized for Datapaths , 1996, VLSI Design.

[19]  N. F. Benschop Symmetric Logic Synthesis with Phase Assignment , 2001 .

[20]  Arrived Virtex-II Pro FPGAs : The Platform for Programmable Systems Has , 2002 .

[21]  K. Leijten-Nowak,et al.  Architecture and implementation of an embedded reconfigurable logic core in CMOS 0.13 /spl mu/m , 2002, 15th Annual IEEE International ASIC/SOC Conference.

[22]  Dwight D. Hill,et al.  The benefits of flexibility in lookup table-based FPGAs , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..