NBTI-aware DVFS: A new approach to saving energy and increasing processor lifetime
暂无分享,去创建一个
[1] John Keane,et al. An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[2] John Sartori,et al. Characterizing the Voltage Scaling Limitations of Razor-based Designs , .
[3] Josep Torrellas,et al. Facelift: Hiding and slowing down aging in multicores , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.
[4] Kaushik Roy,et al. CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[5] Dror G. Feitelson,et al. The workload on parallel supercomputers: modeling the characteristics of rigid jobs , 2003, J. Parallel Distributed Comput..
[6] K. Jenkins,et al. On-Chip circuit for monitoring frequency degradation due to NBTI , 2008, 2008 IEEE International Reliability Physics Symposium.
[7] Todd M. Austin,et al. Ultra low-cost defect protection for microprocessor pipelines , 2006, ASPLOS XII.
[8] M. Orshansky,et al. Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation , 2008, ISQED 2008.
[9] Bin Zhang. Online circuit reliability monitoring , 2009, GLSVLSI '09.
[10] Jaume Abella,et al. Penelope: The NBTI-Aware Processor , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[11] Trevor Mudge,et al. Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..
[12] S. Minehane,et al. Degradation dynamics, recovery, and characterization of negative bias temperature instability , 2005, Microelectron. Reliab..
[13] Luca Benini,et al. Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[14] Soraya Ghiasi,et al. System power management support in the IBM POWER6 microprocessor , 2007, IBM J. Res. Dev..
[15] Scott A. Mahlke,et al. BulletProof: a defect-tolerant CMP switch architecture , 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..
[16] Zhenyu Qi,et al. NBTI resilient circuits using adaptive body biasing , 2008, GLSVLSI '08.
[17] Meeta Sharma Gupta,et al. System level analysis of fast, per-core DVFS using on-chip switching regulators , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.
[18] Lide Zhang,et al. Scheduled voltage scaling for increasing lifetime in the presence of NBTI , 2009, 2009 Asia and South Pacific Design Automation Conference.
[19] Valeria Bertacco,et al. Reversi: Post-silicon validation system for modern microprocessors , 2008, 2008 IEEE International Conference on Computer Design.
[20] Muhammad Ashraful Alam,et al. A comprehensive model of PMOS NBTI degradation , 2005, Microelectron. Reliab..
[21] J. Hicks. 45nm Transistor Reliability , 2008 .
[22] Yu Cao,et al. Predictive Modeling of the NBTI Effect for Reliable Design , 2006, IEEE Custom Integrated Circuits Conference 2006.