White Paper 1: A Case for Lowering Component Level HBM/MM ESD Specifications and Requirements Industry Council on ESD Target Levels

[1]  D. L. Lin,et al.  On the Validity of ESD Threshold Data Obtained Using Commercial Human-Body Model Simulators , 1987, 25th International Reliability Physics Symposium.

[2]  M. Kelly,et al.  A comparison of electrostatic discharge models and failure signatures for CMOS integrated circuit devices , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[3]  E. A. Amerasekera,et al.  ESD in silicon integrated circuits , 1995 .

[4]  S.H. Voldman ESD robustness and scaling implications of aluminum and copper interconnects in advanced semiconductor technology , 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[5]  Akram A. Salman,et al.  Electrostatic discharge induced oxide breakdown characterization in a 0.1 /spl mu/m CMOS technology , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[6]  C. Duvvury,et al.  Non-uniform conduction induced reverse channel length dependence of ESD reliability for silicided NMOS transistors , 2002, Digest. International Electron Devices Meeting,.

[7]  Ming-Dou Ker,et al.  Electrostatic discharge implantation to improve machine-model ESD robustness of stacked NMOS in mixed I/O interface circuits , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

[8]  M. Mergens,et al.  Diode-triggered SCR (DTSCR) for RF-ESD protection of BiCMOS SiGe HBTs and CMOS ultra-thin gate oxides , 2003, IEEE International Electron Devices Meeting 2003.

[9]  C. Duvvury,et al.  Technology scaling effects on the ESD design parameters in sub-100 nm CMOS transistors , 2003, IEEE International Electron Devices Meeting 2003.

[10]  C. Duvvury,et al.  ESD and latch-up reliability for nanometer CMOS technologies , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[11]  R. Gaertner,et al.  From the ESD robustness of products to the system ESD robustness , 2004, 2004 Electrical Overstress/Electrostatic Discharge Symposium.

[12]  A. Marshall,et al.  ESD evaluation of the emerging MuGFET technology , 2005, 2005 Electrical Overstress/Electrostatic Discharge Symposium.

[13]  C. Duvvury,et al.  Analysis of ESD protection components in 65nm CMOS technology: Scaling perspective and impact on ESD design window , 2005, 2005 Electrical Overstress/Electrostatic Discharge Symposium.

[14]  S. Voldman White Paper II Trends in Semiconductor Technology and ESD Testing ESD Association September 2006 , 2006 .

[15]  R. Gartner,et al.  Cable discharges into communication interfaces , 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium.

[16]  B. Baumert,et al.  ESD MM Failures Resulting from Transient Reverse Currents , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[17]  T. Smedes,et al.  Relations between system level ESD and (vf-)TLP , 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium.

[18]  A. Bravaix,et al.  Ultra-thin gate oxide reliability in the ESD time domain , 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium.

[19]  C. Duvvury,et al.  Unique ESD Failure Mechanism in a MuGFET Technology , 2006, 2006 International Electron Devices Meeting.

[20]  R. Gaertner Do we expect ESD failures in an EPA designed according to international standards? The need for a process related risk analysis , 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).