The Primary Instruction Pipelin

In Chapter 2 we saw how the MU5 Processor developed into two pipeline systems, the Primary and Secondary Instruction Pipelines. In this chapter we shall follow the flow of instructions through the units which constitute the Primary Instruction Pipeline (figure 4.1). The Primary Instruction Pipeline operates at a maximum rate of one instruction per 50 ns. This performance is achieved by dividing each unit into a number of stages, each of which can complete its part of the instruction processing within the 50 ns period and then accept the next instruction [12]. The design is presented in some detail to illustrate how conceptual elegance sometimes has to be compromised in order to achieve practical solutions.