Remote and partial reconfiguration of FPGAs: tools and trends

This work describes the implementation of digital reconfigurable systems (DRS) using commercial FPGA devices. This paper has three main goals. The first one is to present the trend of DRS, highlighting the problems and solutions of each DRS generation. The second goal is to present in detail the configuration architecture of a commercial FPGA family allowing DRS implementation. The last goal is to present a set of tools for remote and partial reconfiguration developed for this FPGA family. Even though the tools are targeted to a specific device, their building principles may easily be adapted to other FPGA families, if they have an internal architecture enabling partial reconfiguration. The main contribution of the paper is the tool-set proposed to manipulate cores using partial reconfiguration in existing FPGA.

[1]  Pascal Benoit,et al.  Highly scalable dynamically reconfigurable systolic ring-architecture for DSP applications , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[2]  Jonathan Rose,et al.  The Transmogrifier-2: a 1 million gate rapid-prototyping system , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Vivek Sarkar,et al.  Baring It All to Software: Machines , 1997 .

[4]  Ian Page,et al.  Reconfigurable processor architectures , 1996, Microprocess. Microsystems.

[5]  Seth Copen Goldstein,et al.  PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.

[6]  John Wawrzynek,et al.  Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial , 2000 .

[7]  John W. Lockwood,et al.  Using PARBIT to Implement Partial Run-Time Reconfigurable Systems , 2002, FPL.

[8]  John Wawrzynek,et al.  Stream Computations Organized for Reconfigurable Execution (SCORE) Extended Abstract , 2000 .

[9]  Vivek Sarkar,et al.  Baring It All to Software: Raw Machines , 1997, Computer.

[10]  Moshe Sipper,et al.  Static and Dynamic Configurable Systems , 1999, IEEE Trans. Computers.

[11]  Mark Shand,et al.  Programmable active memories: reconfigurable systems come of age , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[12]  S. Perissakis,et al.  Embedded DRAM for a reconfigurable array , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[13]  Michael J. Wirthlin,et al.  DISC: the dynamic instruction set computer , 1995, Optics East.

[14]  Steven A. Guccione,et al.  Automated extraction of run-time parameterisable cores from programmable device configurations , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

[15]  Reiner W. Hartenstein,et al.  A decade of reconfigurable computing: a visionary retrospective , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[16]  André DeHon,et al.  FCCM ’ 94-- IEEE Workshop on FPGAs for Custom Computing Machines April 10-13 , Napa , CA DPGA-Coupled Microprocessors : Commodity ICs for the Early 21 st Century , 2007 .

[17]  Daniel P. Lopresti,et al.  SPLASH: A Reconfigurable Linear Logic Array , 1990, ICPP.

[18]  Steve McKeever,et al.  Pebble: A Language for Parametrised and Reconfigurable Hardware Design , 1998, FPL.

[19]  Mike Peattie Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations , 2000 .

[20]  Marco Platzner,et al.  Partially Reconfigurable Cores for Xilinx Virtex , 2002, FPL.

[21]  Harvey F. Silverman,et al.  Processor reconfiguration through instruction-set metamorphosis , 1993, Computer.

[22]  AgarwalAnant,et al.  Baring It All to Software , 1997 .

[23]  I. Xilinx Virtex series configuration architecture user guide , 2000 .

[24]  John Wawrzynek,et al.  The Garp Architecture and C Compiler , 2000, Computer.