A 58–65 GHz Neutralized CMOS Power Amplifier With PAE Above 10% at 1-V Supply

A 60-GHz band, three-stage pseudo-differential power amplifier (PA) is implemented with input and output baluns on-chip. Each stage consists of a neutralized common-source amplifier pair. Neutralization mitigates the intrinsic gate-drain feedback of each transistor for increased power gain and reverse isolation. Shielded transformers couple the gain stages and allow low supply voltage operation. Fabricated in a 65-nm bulk CMOS process, the measured small-signal gain of the 0.13 × 0.41 mm2 PA is 16 dB at 60 GHz with 3-dB bandwidth more than 8.5 GHz, while consuming 50 mW from a 1-V supply. Reverse isolation is better than 42 dB from 55 to 65 GHz. Maximum saturated output power is 11.5 dBm with a peak PAE of 15.2% measured at 62 GHz; from 58 to 65 GHz, the measured PAE is above 10%.

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