Parallel block detection, synchronization and hypothesis decision in digital receivers for communications over frequency-selective fading radio channels

In this paper, we are concerned with robust reception of data transmitted over a frequency-selective fading radio channel. Acceptable bit error performance is to be achieved for channels with may exhibit either a short channel impulse response (CIR) but fast fading (state A); or a long CIR but slow fading (state B). Since the channel state is a priori unknown, the concept of parallel receiver operation is adopted where two digital receivers, each tailored to its respective channel state hypothesis (A or B), are performing block synchronization and detection in parallel. Following parallel detection, posterior hypothesis decision is performed based on a nonlinear symbol decision quality metric. A design example of a digital HF receiver for uncoded 8-PSK modulation is presented. Despite the parallel receiver concept, the entire receiver is of remarkably low complexity which has enabled the implementation in integer arithmetic on a single DSP chip. Bit error simulation results are shown that demonstrate the practicability and robustness of the receiver implementation for a wide range of channel conditions.