Exploring the Mysteries of System-Level Test

System-level test, or SLT, is an increasingly important process step in today’s integrated circuit testing flows. Broadly speaking, SLT aims at executing functional workloads in operational modes. In this paper, we consolidate available knowledge about what SLT is precisely and why it is used despite its considerable costs and complexities. We discuss the types or failures covered by SLT, and outline approaches to quality assessment, test generation and root-cause diagnosis in the context of SLT. Observing that the theoretical understanding for all these questions has not yet reached the level of maturity of the more conventional structural and functional test methods, we outline new and promising directions for methodical developments leveraging on recent findings from software engineering.

[1]  Paolo Bernardi,et al.  A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoC , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[2]  Srikanth Venkataraman,et al.  Poirot: Applications of a Logic Fault Diagnosis Tool , 2001, IEEE Des. Test Comput..

[3]  Hans-Joachim Wunderlich,et al.  Adaptive Debug and Diagnosis without Fault Dictionaries , 2007, ETS.

[4]  Krishnendu Chakrabarty,et al.  Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation , 2019, 2019 IEEE International Test Conference (ITC).

[5]  Farzan Fallah,et al.  Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Xin Li,et al.  Fine-Grained Adaptive Testing Based on Quality Prediction , 2018, 2018 IEEE International Test Conference (ITC).

[7]  Peter C. Maxwell,et al.  Comparing functional and structural tests , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[8]  Bernd Becker,et al.  Variation-aware deterministic ATPG , 2014, 2014 19th IEEE European Test Symposium (ETS).

[9]  Tobias Schmid,et al.  Using Data Flow-Based Coverage Criteria for Black-Box Integration Testing of Distributed Software Systems , 2019, 2019 12th IEEE Conference on Software Testing, Validation and Verification (ICST).

[10]  Giovanni Squillero,et al.  New evolutionary techniques for test-program generation for complex microprocessor cores , 2005, GECCO '05.

[11]  M. Sonza Reorda,et al.  Applicative System Level Test introduction to Increase Confidence on Screening Quality , 2020, 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

[12]  Mehdi Baradaran Tahoori,et al.  Post Silicon Debugging of Electrical Bugs Using Trace Buffers , 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

[13]  Melvin A. Breuer,et al.  Switch-level delay test , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[14]  Luis D. Rojas,et al.  Effectively Using Machine Learning to Expedite System Level Test Failure Debug , 2019, 2019 IEEE International Test Conference (ITC).

[15]  Melvin A. Breuer,et al.  Modeling and simulation for crosstalk aggravated by weak-bridge defects between on-chip interconnects , 2004, 13th Asian Test Symposium.

[16]  Ilia Polian.  Power Supply Noise: Causes, Effects, and Testing , 2010, J. Low Power Electron..

[17]  V. Kamakoti,et al.  Power Virus Generation Using Behavioral Models of Circuits , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[18]  Fangming Ye,et al.  Board-Level Functional Fault Identification using Streaming Data , 2019, 2019 IEEE 37th VLSI Test Symposium (VTS).

[19]  Friedrich Hapke,et al.  Defect-Oriented Test: Effectiveness in High Volume Manufacturing , 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Bernd Becker,et al.  A Flexible Framework for the Automatic Generation of SBST Programs , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Harry H. Chen,et al.  Beyond structural test, the rising need for system-level test , 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

[22]  Adit D. Singh,et al.  An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures , 2019, 2019 IEEE International Test Conference (ITC).

[23]  M. Sonza Reorda,et al.  Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test , 2019, 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

[24]  Andreas Spillner,et al.  Test criteria and coverage measures for software integration testing , 1995, Software Quality Journal.

[25]  John P. Hayes,et al.  High-level delay test generation for modular circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[26]  Terrence Huat Hin Tan,et al.  Adaptive test method on production system-level testing (SLT) to optimize test cost, resources and defect parts per million (DPPM) , 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

[27]  Jacob A. Abraham,et al.  Test Generation for Microprocessors , 1980, IEEE Transactions on Computers.