Proof theory and a validation condition generator for VHDL

We present a Hoare-style programming logic for VHDL together with a succinctPROLOG implementation which acts as a validation condition generator. The logic is based on a particularly simple formalization of the language as a pure side-effect on an infinite time-sequence of states. The PROLOG program transforms logical assertions to their prerequisite hypotheses, thus reducing formal verification to a proof that certain initial conditions hold.