The Impact of Self-Heating on HCI Reliability in High-Performance Digital Circuits

While many groups attribute the greatly accelerated (i.e., excess) HCI degradation in modern transistors to the difference between the peak temperature and the average temperature (<inline-formula> <tex-math notation="LaTeX">${\Delta } {T}_{ {L,{\rm{Diff}}}}=\Delta {T}_{ {L}}^{\mathrm {pk}}-\Delta {T}_{{L}}^{\mathrm {avg}}\mathbf {\gg 0}$ </tex-math></inline-formula>) in self-heated FinFETs and other multigate transistors under dc or low-frequency stress, others find no evidence of the <inline-formula> <tex-math notation="LaTeX">${\Delta } {T}_{ {L,{\rm{Diff}}}}$ </tex-math></inline-formula>-related excess degradation for ICs operating at high frequencies. In this letter, we resolve the puzzle by using a hierarchical electro-thermal device-circuit predictive model for HCI degradation to demonstrate that <inline-formula> <tex-math notation="LaTeX">${\Delta } {T}_{ {L,{\rm{Diff}}}} {\to } {{0}}$ </tex-math></inline-formula> beyond a technology-specific transition frequency (<inline-formula> <tex-math notation="LaTeX">${\omega }_{ {c}}$ </tex-math></inline-formula>), and therefore, excess HCI degradation disappears at <inline-formula> <tex-math notation="LaTeX">${\omega \gg }{\omega }_{ {c}}$ </tex-math></inline-formula>. The proposed analytical model directly correlates HCI performance to power pulse trains characterized by frequency (<inline-formula> <tex-math notation="LaTeX">$ {f}$ </tex-math></inline-formula>) and power duty cycle (<inline-formula> <tex-math notation="LaTeX">$\boldsymbol{\xi }$ </tex-math></inline-formula>) of a digital circuit. Self-heating will continue to reduce HCI-lifetime of surround gate transistors due to the increase of average temperature (<inline-formula> <tex-math notation="LaTeX">${\Delta } {T}_{ {L}}^{\mathrm {avg}}$ </tex-math></inline-formula>), but the excess degradation caused by <inline-formula> <tex-math notation="LaTeX">${\Delta } {T}_{ {L,{\rm{Diff}}}}$ </tex-math></inline-formula> will not be a concern for high-speed digital circuits.

[1]  Chenming Hu,et al.  SOI thermal impedance extraction methodology and its significance for circuit simulation , 2001 .

[2]  William Redman-White,et al.  Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques , 1996 .

[3]  Xing Zhang,et al.  Characterization of self-heating leads to universal scaling of HCI degradation of multi-fin SOI FinFETs , 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).

[4]  K. Wu,et al.  Self-heating effect in FinFETs and its impact on devices reliability characterization , 2014, 2014 IEEE International Reliability Physics Symposium.

[5]  A. Mercha,et al.  Self-heating on bulk FinFET from 14nm down to 7nm node , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[6]  M. A. Wahab,et al.  Direct Observation of Self-Heating in III–V Gate-All-Around Nanowire MOSFETs , 2015, IEEE Transactions on Electron Devices.

[7]  X. Federspiel,et al.  HCI Lifetime Correction Based on Self-Heating Characterization for SOI Technology , 2007, IEEE Transactions on Device and Materials Reliability.

[8]  Steven W. Mittl,et al.  Self-heating and its implications on hot carrier reliability evaluations , 2015, 2015 IEEE International Reliability Physics Symposium.

[9]  N. Xu,et al.  Investigation of Self-Heating Effect on Hot Carrier Degradation in Multiple-Fin SOI FinFETs , 2015, IEEE Electron Device Letters.

[10]  M. A. Wahab,et al.  3D Modeling of Spatio-temporal Heat-transport in III-V Gate-all-around Transistors Allows Accurate Estimation and Optimization of Nanowire Temperature , 2015, IEEE Transactions on Electron Devices.

[11]  Naoto Horiguchi,et al.  Origins and implications of increased channel hot carrier variability in nFinFETs , 2015, 2015 IEEE International Reliability Physics Symposium.

[12]  S. Natarajan,et al.  Self-heat reliability considerations on Intel's 22nm Tri-Gate technology , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[13]  Seungjin Choo,et al.  Hot carrier reliability characterization in consideration of self-heating in FinFET technology , 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).