Statistics-Based Digital Background Calibration of Residue Amplifier Nonlinearity in Pipelined ADCs

In this paper, a statistics-based digital background calibration technique for pipelined analog-to-digital converters (ADCs) is presented. This technique employs the residue voltage probability distribution to continuously estimate and digitally eliminate the conversion errors resulted from the residue amplifier gain error and third-order nonlinearity. In order to remove the conversion errors, the proposed method evaluates and corrects the digitized residue probability distribution exploiting a two-level pseudorandom-noise sequence. Behavioral simulation results are provided for a 12-bit pipelined ADC architecture to validate the effectiveness of this scheme. The required number of conversions for convergence is approximately $5\times 10^{6}$ . With calibration, the signal-to-noise and distortion ratio is improved from 49.9 to 70.9 dB.

[1]  Marie-Minerve Louërat,et al.  Split ADC Based Fully Deterministic Multistage Calibration for High Speed Pipeline ADCs , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Franco Maloberti,et al.  Online calibration of a Nyquist-rate analog-to-digital converter using output code-density histograms , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  David A. Johns,et al.  A Low-Power Capacitive Charge Pump Based Pipelined ADC , 2010, IEEE Journal of Solid-State Circuits.

[4]  Hae-Seung Lee,et al.  Background Calibration of Pipelined ADCs Via Decision Boundary Gap Estimation , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  D. Richard Brown,et al.  Digital Background-Calibration Algorithm for “Split ADC” Architecture , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Franco Maloberti,et al.  A Pseudorandom Number Generator Based on Time-Variant Recursion of Accumulators , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  Frank M. L. van der Goes,et al.  A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration , 2015, IEEE Journal of Solid-State Circuits.

[8]  Tohid Moosazadeh,et al.  A Single Channel Split ADC Structure for Digital Background Calibration in Pipelined ADCs , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Bernard C. Levy A Propagation Analysis of Residual Distributions in Pipeline ADCs , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Ian Galton,et al.  Suppression of Quantization-Induced Convergence Error in Pipelined ADCs With Harmonic Distortion Correction , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  Hossein Shamsi,et al.  Fully differential charge-pump comparator-based pipelined ADC in 90 nm CMOS , 2016, Microelectron. J..

[12]  B. Murmann,et al.  A 12 b 75 MS/s pipelined ADC using open-loop residue amplification , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[13]  Mohammad Yavari,et al.  Digital Calibration of DAC Unit Elements Mismatch in Pipelined ADCs , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[14]  Mohammad Yavari,et al.  Digital Background Calibration With Histogram of Decision Points in Pipelined ADCs , 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

[15]  Boris Murmann,et al.  System embedded ADC calibration for OFDM receivers , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Nan Sun Exploiting Process Variation and Noise in Comparators to Calibrate Interstage Gain Nonlinearity in Pipelined ADCs , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  Ian Galton Digital cancellation of D/A converter noise in pipelined A/D converters , 2000 .

[18]  Hamidreza Mafi,et al.  Digital Background Calibration of Residue Amplifier Non-idealities in Pipelined ADCs , 2016, Circuits Syst. Signal Process..

[19]  Dong Wang,et al.  Background interstage gain calibration technique for pipelined ADCs , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[20]  Ian Galton,et al.  A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction , 2009, IEEE Journal of Solid-State Circuits.

[21]  Behzad Razavi,et al.  A 12-Bit 200-MHz CMOS ADC , 2009, IEEE Journal of Solid-State Circuits.

[22]  Tohid Moosazadeh,et al.  A Calibration Technique for Pipelined ADCs Using Self-Measurement and Histogram-Based Test Methods , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[23]  Boris Murmann,et al.  Digital Domain Measurement and Cancellation of Residue Amplifier Nonlinearity in Pipelined ADCs , 2007, IEEE Transactions on Instrumentation and Measurement.

[24]  Jianhui Wu,et al.  Digital Background Calibration Techniques for Pipelined ADC Based on Comparator Dithering , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

[25]  Ángel Rodríguez-Vázquez,et al.  Equalization-Based Digital Background Calibration Technique for Pipelined ADCs , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[26]  B. Razavi,et al.  A 10-Bit 500-MS/s 55-mW CMOS ADC , 2009, IEEE Journal of Solid-State Circuits.

[27]  Ian Galton,et al.  Digital Background Correction of Harmonic Distortion in Pipelined ADCs , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[28]  B. Murmann,et al.  A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification , 2009, IEEE Journal of Solid-State Circuits.

[29]  Boris Murmann,et al.  A 12-b, 30-MS/s, 2.95-mW Pipelined ADC Using Single-Stage Class-AB Amplifiers and Deterministic Background Calibration , 2012, IEEE Journal of Solid-State Circuits.

[30]  Hossein Shamsi,et al.  Resilient design of current steering DACs using a transistor level approach , 2017 .