Design for test and reliability in ultimate CMOS

This session brings together specialists from the DfT, DfY and DfR domains that will address key problems together with their solutions for the 14 nm node and beyond, dealing with extremely complex chips affected by high defect levels, unpredictable and heterogeneous timing behavior, circuit degradation over time, including extreme situations related with the ultimate CMOS nodes, where all processor nodes, routers and links of single-chip massively parallel tera-device processors could comprise timing faults (such as delay faults or clock skews); a large percentage of these parts are affected by catastrophic failures; all parts experience significant performance degradations over time; and new catastrophic failures occur at low MTBF.

[1]  David M. Bull,et al.  RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance , 2009, IEEE Journal of Solid-State Circuits.

[2]  M. Nicolaidis,et al.  Cost reduction and evaluation of a temporary faults detecting technique , 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

[3]  Radu Marculescu,et al.  Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Nadir Achouri,et al.  Dynamic Data-bit Memory Built-In Self- Repair , 2003, ICCAD.

[5]  Yervant Zorian.  Embedded memory test and repair: infrastructure IP for SOC yield , 2002, Proceedings. International Test Conference.

[6]  Takayasu Sakurai,et al.  Built-in self-repair circuit for high-density ASMIC , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[7]  Jacques Henri Collet,et al.  Self-Configuration and Reachability Metrics in Massively Defective Multiport Chips , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[8]  Nacer-Eddine Zergainoh,et al.  Variability-aware task mapping strategies for many-cores processor chips , 2011, 2011 IEEE 17th International On-Line Testing Symposium.

[9]  Srivaths Ravi,et al.  Systematic Software-Based Self-Test for Pipelined Processors , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Yervant Zorian.  Embedded Memory Test & Repair : Infrastructure IP for SOC Yield Yervant Zorian Virage Logic , 2002 .

[11]  K.A. Bowman,et al.  Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance , 2009, IEEE Journal of Solid-State Circuits.

[12]  Bruce G. Mealey,et al.  IBM POWER6 reliability , 2007, IBM J. Res. Dev..

[13]  Lorena Anghel,et al.  A diversified memory built-in self-repair approach for nanotechnologies , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[14]  Michael Nicolaidis.  Time redundancy based soft-error tolerance to rescue nanometer technologies , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[15]  Luca Benini,et al.  A low-overhead fault tolerance scheme for TSV-based 3D network on chip links , 2008, ICCAD 2008.

[16]  Michael Nicolaidis,et al.  Circuit-Level Soft-Error Mitigation , 2011 .

[17]  Nacer-Eddine Zergainoh,et al.  Self-Recovering Parallel Applications in Multi-core Systems , 2011, 2011 IEEE 10th International Symposium on Network Computing and Applications.

[18]  Nacer-Eddine Zergainoh,et al.  Fault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-cores Systems , 2010, 2010 Ninth IEEE International Symposium on Network Computing and Applications.

[19]  David Blaauw,et al.  Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[20]  Michael Nicolaidis,et al.  Enhanced self-configurability and yield in multicore grids , 2009, 2009 15th IEEE International On-Line Testing Symposium.

[21]  Radu Marculescu,et al.  FARM: Fault-aware resource management in NoC-based multiprocessor platforms , 2011, 2011 Design, Automation & Test in Europe.

[22]  Luca Benini,et al.  A low-overhead fault tolerance scheme for TSV-based 3D network on chip links , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[23]  Lorena Anghel,et al.  Improving the scalability of checkpoint recovery for networks-on-chip , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[24]  Lorena Anghel,et al.  Cost reduction and evaluation of temporary faults detecting technique , 2000, DATE '00.

[25]  Nacer-Eddine Zergainoh,et al.  Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor , 2011, 2011 Sixteenth IEEE European Test Symposium.

[26]  Vladimir Pasca,et al.  CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems , 2012, J. Electron. Test..

[27]  Nacer-Eddine Zergainoh,et al.  A fault-tolerant deadlock-free adaptive routing for on chip interconnects , 2011, 2011 Design, Automation & Test in Europe.

[28]  Jun Zhou,et al.  Software-Based Self-Test of Processors under Power Constraints , 2006, Proceedings of the Design Automation & Test in Europe Conference.