Detecting delay flaws by very-low-voltage testing

The detectability of delay flaws can be improved by testing CMOS IC's with a very low supply voltage-between 2 and 2.5 times the threshold voltage V/sub t/ of the transistors. A delay flaw is a defect that causes a local timing failure but the failure is not severe enough to cause malfunctioning. Delay flaws caused by degraded signals and gates with lower drive capability than expected are considered. This paper investigates the voltage dependence of the effects of delay flaws and derives the test conditions for them.

[1]  P. Bannon,et al.  A 433 MHz 64 b quad issue RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[2]  Chenming Hu,et al.  Hot-electron-induced MOSFET degradation—Model, monitor, and improvement , 1985, IEEE Transactions on Electron Devices.

[3]  H. Sanchez,et al.  A 200 MHz 2.5 V 4 W superscalar RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[4]  Charles F. Hawkins,et al.  THE BEHAVIOR AND TESTING IMPLICATIONS OF CMOS IC LOGIC GATE OPEN CIRCUITS , 1991, 1991, Proceedings. International Test Conference.

[5]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[6]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[7]  Resve Saleh,et al.  Analysis and Design of Digital Integrated Circuits , 1983 .

[8]  Richard T. Witek,et al.  A 160 MHz 32 b 0.5 W CMOS RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[9]  J. Shott,et al.  A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOS , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[10]  Theodore I. Kamins,et al.  Device Electronics for Integrated Circuits , 1977 .

[11]  Edward J. McCluskey,et al.  DELAY TESTING OF DIGITAL CIRCUITS BY OUTPUT WAVEFORM ANALYSIS , 1991, 1991, Proceedings. International Test Conference.

[12]  Chenming Hu,et al.  Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement , 1985, IEEE Journal of Solid-State Circuits.

[13]  Piero Franco.  Testing Digital Circuits for Timing Failures by Output Waveform Analysis , 1994 .

[14]  Sung-Mo Kang,et al.  Hot-Carrier Reliability Of MOS VLSI Circuits , 1993 .

[15]  Edward J. McCluskey,et al.  Quantitative analysis of very-low-voltage testing , 1996, Proceedings of 14th VLSI Test Symposium.

[16]  Charles F. Hawkins,et al.  Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs , 1985, ITC.

[17]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[18]  Edward J. McCluskey,et al.  Very-low-voltage testing for weak CMOS logic ICs , 1993, Proceedings of IEEE International Test Conference - (ITC).

[19]  Yuan Taur,et al.  An ultra-low power 0.1 /spl mu/m CMOS , 1994, Proceedings of 1994 VLSI Technology Symposium.