论文信息 - A 150MS/s 8b 71mW time-interleaved ADC in 0.18/spl mu/m CMOS

A 150MS/s 8b 71mW time-interleaved ADC in 0.18/spl mu/m CMOS

This paper presents a 150 MS/s 8 bit time-interleaved ADC which has been built in 0.18 /spl mu/m CMOS. Segmentation of the track-and-hold into separate circuits, driving the 1st stage comparators and two interleaved residue paths, together with signal scaling, results in a 45.4 dB SNDR for an 80 MHz input frequency, while dissipating 71 mW from a 1.8 V supply.

B.A. Wooley | S. Limotyrakis | S.D. Kulchycki | D. Su

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