A 40 Mbit/s soft output Viterbi decoding ASIC

Decoding algorithms that make not only use of soft quantized inputs but also deliver soft decision outputs have attracted considerable interest. This was motivated by newly developed soft output algorithms with reduced complexity and advances in VLSI technology. The authors present, to the best of their knowledge, the first high speed VLSI implementation of the soft output Viterbi algorithm. The 43 mm/sup 2/ chip is designed for a 16 state convolutional code, and tested samples achieved a throughput of 50 Mbit/s. It is thus demonstrated that transmission schemes using soft output decoding can be considered practical even at very high throughputs. Since such decoding systems are more complex to design than hard output systems special emphasis is placed on the employed design methodology.

[1]  Jens Sparsø,et al.  An area-efficient path memory structure for VLSI implementation of high speed Viterbi decoders , 1991, Integr..

[2]  M. Nasiri-Kenari,et al.  Matched spectral-null codes with soft-decision outputs , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[3]  Peter Adam Hoeher.  TCM on frequency-selective fading channels: a comparison of soft-output probabilistic equalizers , 1990, [Proceedings] GLOBECOM '90: IEEE Global Telecommunications Conference and Exhibition.

[4]  Peter Adam Hoeher,et al.  Separable MAP "filters" for the decoding of product and concatenated codes , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[5]  Shuji Kubota,et al.  DSD (Double Soft Decision) Concatenated FEC Scheme in Mobile Satellite Communication Systems , 1992, IEEE J. Sel. Areas Commun..

[6]  Carl-Erik W. Sundberg,et al.  Advanced techniques for modulation, error correction, channel equalization, and diversity , 1993, AT&T Technical Journal.

[7]  H. Meyr,et al.  High-speed VLSI architectures for soft-output Viterbi decoding , 1992, [1992] Proceedings of the International Conference on Application Specific Array Processors.

[8]  A. Glavieux,et al.  Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[9]  Heinrich Meyr,et al.  High-speed VLSI architectures for soft-output viterbi decoding , 1994, J. VLSI Signal Process..

[10]  E. Offer,et al.  Improving the standard coding system for deep space missions , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[11]  H. Meyr,et al.  Soft-output Viterbi decoding: VLSI implementation issues , 1993, IEEE 43rd Vehicular Technology Conference.

[12]  John Cocke,et al.  Optimal decoding of linear codes for minimizing symbol error rate (Corresp.) , 1974, IEEE Trans. Inf. Theory.

[13]  Peter Adam Hoeher.  Advances in soft-output decoding , 1993, Proceedings of GLOBECOM '93. IEEE Global Telecommunications Conference.

[14]  H. Meyr,et al.  Systematic design optimization of a competitive soft-concatenated decoding system , 1993, Proceedings of IEEE Workshop on VLSI Signal Processing.

[15]  Claude Berrou,et al.  A low complexity soft-output Viterbi decoder architecture , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.