A BIST design of structured arrays with fault-tolerant layout

A BIST (built-in self-test)-compatible method for the design, layout, and test of structured logic arrays is presented. The layout is analyzed for realistic faults in the conducting layers of a typical CMOS process. It is found that only one-third of the faults while occurring as a result of random spot defects are classical stuck faults while others have to be manipulated by the appropriate test vectors to manifest themselves as stuck faults further down in the circuit. Many of these faults are detected by the test method adopted without any special provisions in the circuit. This technique eliminates the need for placing shift registers and exclusive-OR gates on the product lines of the array.<<ETX>>

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