Improving Constant-Coefficient Multiplier Verification by Partial Product Identification
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[1] Andrew D. Booth,et al. A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .
[2] Algirdas Avizienis,et al. Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..
[3] Dominik Stoffel,et al. Verification of integer multipliers on the arithmetic bit level , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).
[4] Jiunn-Chern Chen,et al. Equivalence checking of integer multipliers , 2001, ASP-DAC '01.
[5] Harvey L. Garner,et al. Number Systems and Arithmetic , 1965, Adv. Comput..
[6] A. Avizeinis,et al. Signed Digit Number Representations for Fast Parallel Arithmetic , 1961 .
[7] Kwang-Ting Cheng,et al. Induction-based gate-level verification of multipliers , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).
[8] Kai Hwang,et al. Computer arithmetic: Principles, architecture, and design , 1979 .
[9] Christopher S. Wallace,et al. A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..
[10] Randal E. Bryant,et al. Verification of Arithmetic Circuits with Binary Moment Diagrams , 1995, 32nd Design Automation Conference.
[11] Masahiro Fujita,et al. Verification of Arithmetic Circuits by Comparing Two Similar Circuits , 1996, CAV.
[12] G. Clark,et al. Reference , 2008 .
[13] Randal E. Bryant,et al. *PHDD: an efficient graph representation for floating point circuit verification , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[14] Dominik Stoffel,et al. Reasoning in Boolean Networks - Logic Synthesis and Verification Using Testing Techniques , 1997, Frontiers in electronic testing.
[15] Daniel Brand. Verification of large synthesized designs , 1993, ICCAD.