Circuit techniques for high speed communication

This article analyses the technology limits for designing integrated circuits for high-speed communication applications. It includes discussions on channel and protocol processing and CMOS circuit techniques.

[1]  A. Edman,et al.  SDH 10 Gb/s regenerator framer in 0.6 /spl mu/m CMOS , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[2]  C. Svensson,et al.  10-100 Gb/s throughput CMOS techniques , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[3]  C. Svensson,et al.  A VLSI architecture for an 80 Gb/s ATM switch core , 1996, 1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon.

[4]  Christer Svensson,et al.  Digital multiphase clock/pattern generator , 1999 .