Evaluating the Yield of Repairable

An accurate yield evaluation is essential in selecting redundancy allocation and testing strategies for memories. Yield evaluation can resolve the many issues revolving around cost- effective built-in self-test (BIST) and automatic test equipment (ATE)-based solutions for a higher test transparency. In this paper, two yield-calculation methodologies for SRAM arrays are proposed. General yield expressions for VLSI chips are initially presented. The regular and repetitive structure of an SRAM array is exploited, and substantial yield improvements can be achieved by the introduction of redundancy. Two repair yield-evaluation methods for one-dimensional redundant memory arrays are in- troduced and compared for ATE application. The first method is based on the sum of the probabilities of all repairable fault patterns; the second method is based on Markov modeling. Using industrial data, it is shown that these methods are applicable to ATE usage under different conditions of defect rate in the possible defects. Different features of the proposed methods are discussed. Index Terms—Automatic test equipment (ATE), manufacturing, Markov modeling, redundancy, SRAM, yield.

[1]  C. H. Stapper,et al.  Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product , 1980, IBM J. Res. Dev..

[2]  Fabrizio Lombardi,et al.  Simulation of reconfigurable memory core yield , 2004, GLSVLSI '04.

[3]  Bruno Ciciani,et al.  A Markov chain-based yield formula for VLSI fault-tolerant chips , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Gerard A. Allan A comparison of efficient dot throwing and shape shifting extra material critical area estimation , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[5]  Charles H. Stapper,et al.  Large-Area Fault Clusters and Fault Tolerance in VLSI Circuits: A Review , 1989, IBM J. Res. Dev..

[6]  Robert C. Evans,et al.  Testing Repairable RAMs and Mostly Good Memories , 1981, International Test Conference.

[7]  Bruno O. Shubert,et al.  Random variables and stochastic processes , 1979 .

[8]  B. Ciciani,et al.  An improved analytical yield evaluation method for redundant RAM's , 1998, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236).

[9]  Charles H. Stapper,et al.  Modeling of Integrated Circuit Defect Sensitivities , 1983, IBM J. Res. Dev..

[10]  Yervant Zorian,et al.  Built in self repair for embedded high density SRAM , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[11]  Athanasios Papoulis,et al.  Probability, Random Variables and Stochastic Processes , 1965 .

[12]  A. V. Ferris-Prabhu,et al.  Defect size variations and their effect on the critical area of VLSI devices , 1985 .

[13]  Dhiraj K. Pradhan,et al.  Modeling Defect Spatial Distribution , 1989, IEEE Trans. Computers.

[14]  Steven F. Oakland,et al.  On-chip repair and an ATE independent fusing methodology , 2002, Proceedings. International Test Conference.

[15]  S. Tsuchida Test and repair of non-volatile commodity and embedded memories , 2002, Proceedings. International Test Conference.

[16]  W. Kent Fuchs,et al.  Efficient Spare Allocation for Reconfigurable Arrays , 1987 .

[17]  Israel Koren,et al.  A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits , 1993, IEEE Trans. Computers.

[18]  Fabrizio Lombardi,et al.  Yield analysis of compiler-based arrays of embedded SRAMs , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

[19]  Kazutami Arimoto,et al.  Test cost reduction by at-speed BISR for embedded DRAMs , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[20]  Charles H. Stapper LSI yield modeling and process monitoring , 2000, IBM J. Res. Dev..

[21]  B. T. Murphy,et al.  Cost-size optima of monolithic integrated circuits , 1964 .

[22]  John Day A Fault-Driven, Comprehensive Redundancy Algorithm , 1985, IEEE Design & Test of Computers.

[23]  J. Meindl,et al.  A discussion of yield modeling with defect clustering, circuit repair, and circuit redundancy , 1990 .