Semiconductor memory device and method of testing the same

The semiconductor memory device includes a memory core, N number of first data input and output pins, M number of second data input and output pins, the first and the second BIST circuit, the first and the second buffer circuit. First BIST circuit when the test mode signal is active and generates a first test pattern data. A first buffer circuit to the external host through the memory core and the N at least one of the first data input and output pins are respectively coupled between the test mode signal when the active the first test pattern data to the N first data input and output pins outputs. A second buffer circuit corresponding to the memory core and the M number of second data input-output when pins are respectively coupled between the test mode signal is active the M second data input of the first test pattern data output from the host via the at least one of the pins first it receives the second test pattern data. The second BIST circuit is tested when the test mode signal is active to generate the first test pattern data and comparing the second test pattern data. The test pattern data may in particular reduce the test time of the memory device to operate at a high speed of several tens of GHz, by performing the input and output to the memory through the test any plurality of data input-output pin (s) selected in the memory device.