Functional abstraction and formal proof of digital circuits

A discussion is given on the set of tools that has been developed at Bull for functional verification of VLSI circuits. The functional verification process is based on two key concepts. The first one is functional abstraction which consists of automatically producing a functional view of a circuit from a lower level of description that can be either a structural or a layout description. The second one is formal verification that consists of automatically proving that the abstracted view of a circuit is correct with respect to its functional specification given by the circuit designer. The set of tools implementing these concepts is intensively used at Bull by all VLSI circuit designers.<<ETX>>

[1]  Tom Melham,et al.  Abstraction Mechanisms for Hardware Verification , 1988 .

[2]  F. Gourdy,et al.  NOISY: an electrical noise checker for ULSI , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[3]  B. De Loore,et al.  Automatic verification of library-based IC designs , 1991 .

[4]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[5]  Jean Christophe Madre,et al.  Proving circuit correctness using formal comparison between expected and extracted behaviour , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[6]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.