Testing Digital Circuits for Timing Failures by Output Waveform Analysis

Delay testing is done to ensure that a digital circuit functions at the designed speed. Delay testing is complicated by test invalidation and fault detection size. Furthermore, we show that simple delay models are not sufficient to provoke the longest delay through a circuit. Even if all paths are robustly tested, path delay testing cannot guarantee that the circuit functions at the desired speed. Output Waveform Analysis is a new approach for detecting timing failures in digital circuits. Unlike conventional testing where the circuit outputs are sampled, the waveform between samples is analyzed. The motivation is that delay changes affect the shape of the output waveform, and information can be extracted from the waveform to detect timing failures. This is especially useful as a Design-for-Testability technique for Built-In Self-Test or pseudo-random testing environments, where delay tests are difficult to apply and test invalidation is a problem. Stability Checking is a simple form of Output Waveform Analysis. In a fault-free circuit, the outputs are expected to have reached the desired logic values by the time they are sampled, so delay faults can be detected by observing the outputs for any changes after the sampling time. Apart from traditional delay testing, Stability Checking is also useful for on-line or concurrent testing under certain timing restrictions. A padding algorithm was implemented to show that circuits can be efficiently modified to meet the required timing constraints. By analyzing the output waveform before the sampling time, circuits with timing flaws can be detected even before the circuit fails. This is useful in high reliability applications as a screening technique that does not stress the circuit, and for wear-out prediction. A symbolic waveform simulator has been implemented to show the benefits of the proposed Output Waveform Analysis techniques. Practical test architectures have been designed, and various waveform analyzers have been manufactured and tested. These include circuits implemented using the Stanford BiCMOS process, and a design implemented in a 25k gate Test Evaluation Chip Experiment.

[1]  Barry K. Rosen,et al.  Delay test generation. I. Concepts and coverage metrics , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[2]  Kenneth P. Parker.  Integrating design and test : using CAE tools for ATE programming , 1987 .

[3]  M.H. Woods,et al.  MOS VLSI reliability and yield trends , 1986, Proceedings of the IEEE.

[4]  Edward J. McCluskey,et al.  Three-pattern tests for delay faults , 1994, Proceedings of IEEE VLSI Test Symposium.

[5]  Chenming Hu,et al.  Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement , 1985, IEEE Journal of Solid-State Circuits.

[6]  S. M. Reddy,et al.  On the design of path delay fault testable combinational circuits , 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.

[7]  Nagisa Ishiura,et al.  Coded time-symbolic simulation using shared binary decision diagram , 1991, DAC '90.

[8]  Sandip Kundu,et al.  Design of scan-based path delay testable sequential circuits , 1993, Proceedings of IEEE International Test Conference - (ITC).

[9]  Thomas M. Storey,et al.  Delay test simulation , 1977, DAC '77.

[10]  Niraj K. Jha,et al.  Design and synthesis of self-checking VLSI circuits and systems , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[11]  Giovanni De Micheli,et al.  Inserting active delay elements to achieve wave pipelining , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[12]  S. Reddy,et al.  Synthesis of combinational logic circuits for path delay fault testability , 1990, IEEE International Symposium on Circuits and Systems.

[13]  Kurt Keutzer,et al.  Validatable nonrobust delay-fault testable circuits via logic synthesis , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Melvin A. Breuer,et al.  Procedures for Eliminating Static and Dynamic Hazards in Test Generation , 1974, IEEE Transactions on Computers.

[15]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[16]  Trevor York,et al.  Book Review: Principles of CMOS VLSI Design: A Systems Perspective , 1986 .

[17]  K.D. Wagner,et al.  Clock system design , 1988, IEEE Design & Test of Computers.

[18]  Michael D. Ciletti,et al.  A variable observation time method for testing delay faults , 1991, DAC '90.

[19]  Edward J. McCluskey,et al.  Relating aliasing in signature analysis to test length and register design , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[20]  Sudhakar M. Reddy,et al.  On the detection of delay faults , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[21]  Edward J. McCluskey,et al.  DELAY TESTING OF DIGITAL CIRCUITS BY OUTPUT WAVEFORM ANALYSIS , 1991, 1991, Proceedings. International Test Conference.

[22]  Charles R. Kime,et al.  Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open Faults , 1985, International Test Conference.

[23]  Soumitra Bose,et al.  Generation of compact delay tests by multiple path activation , 1993, Proceedings of IEEE International Test Conference - (ITC).

[24]  A. P. Dorey.  Rapid Reliability Assessment of VLSICs , 1990 .

[25]  Robert B. Hitchcock,et al.  Timing Analysis of Computer Hardware , 1982, IBM J. Res. Dev..

[26]  R. Ramaswami,et al.  Book Review: Design and Analysis of Fault-Tolerant Digital Systems , 1990 .

[27]  Srinivas Patil,et al.  Skewed-Load Transition Test: Part II, Coverage , 1992, Proceedings International Test Conference 1992.

[28]  Edward J. McCluskey,et al.  Bounds on signature analysis aliasing for random testing , 1991, [1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium.

[29]  Sudhakar M. Reddy,et al.  On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[30]  Masakazu Shoji,et al.  Theory of CMOS Digital Circuits and Circuit Failures , 1992 .

[31]  Kurt Keutzer,et al.  Design of integrated circuits fully testable for delay-faults and multifaults , 1990, Proceedings. International Test Conference 1990.

[32]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[33]  Irith Pomeranz,et al.  An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[34]  John J. Shedletsky,et al.  An Experimental Delay Test Generator for LSI Logic , 1980, IEEE Transactions on Computers.

[35]  M. Ray Mercer,et al.  The interdependence between delay-optimization of synthesized networks and testing , 1991, 28th ACM/IEEE Design Automation Conference.

[36]  P. Banerjee,et al.  Reliability driven logic synthesis of multilevel circuits , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[37]  Irith Pomeranz,et al.  At-speed delay testing of synchronous sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[38]  Edward J. McCluskey,et al.  REFINED BOUNDS ON SIGNATURE ANALYSIS ALIASING FOR RANDOM TESTING , 1991, 1991, Proceedings. International Test Conference.

[39]  Edward J. McCluskey,et al.  Concurrent Error Detection Using Watchdog Processors - A Survey , 1988, IEEE Trans. Computers.

[40]  Charles F. Hawkins,et al.  Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs , 1985, ITC.

[41]  Charles F. Hawkins,et al.  Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs , 1986, ITC.

[42]  Sudhakar M. Reddy,et al.  On Multiple Path Propagating Tests for Path Delay Faults , 1991, 1991, Proceedings. International Test Conference.

[43]  Robert K. Brayton,et al.  Multilevel logic synthesis , 1990, Proc. IEEE.

[44]  Robert K. Brayton,et al.  Minimum padding to satisfy short path constraints , 1993, ICCAD.

[45]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.

[46]  Dhiraj K. Pradhan,et al.  A method to derive compact test sets for path delay faults in combinational circuits , 1993, Proceedings of IEEE International Test Conference - (ITC).

[47]  Edward J. McCluskey,et al.  WSIM: A Symbolic Waveform Simulator , 1994 .

[48]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[49]  Melvin A. Breuer.  The Effects of Races, Delays, and Delay Faults on Test Generation , 1974, IEEE Transactions on Computers.

[50]  Orest Bula,et al.  Gross delay defect evaluation for a CMOS logic design system product , 1990 .

[51]  Dennis V. Heinbuch,et al.  CMOS3 cell library , 1988 .

[52]  Barry K. Rosen,et al.  Efficient Fault Simulation of CMOS Circuits with Accurate Models , 1986, ITC.

[53]  Mark W. Levi,et al.  CMOS Is Most Testable , 1981, International Test Conference.

[54]  Robert C. Aitken,et al.  Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds , 1993, Proceedings of IEEE International Test Conference - (ITC).

[55]  Kwang-Ting Cheng,et al.  Delay testing for non-robust untestable circuits , 1993, Proceedings of IEEE International Test Conference - (ITC).

[56]  Fabian Klass,et al.  Use of CMOS Technology in Wave Pipelining , 1992, The Fifth International Conference on VLSI Design.

[57]  Edward J. McCluskey,et al.  An Experimental Chip to Evaluate Test Techniques Part 1: Description of Experiment , 1994 .

[58]  M. Ray Mercer,et al.  Delay Testing Quality in Timing-Optimized Designs , 1991, 1991, Proceedings. International Test Conference.

[59]  Nagisa Ishiura,et al.  Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits , 1989, 26th ACM/IEEE Design Automation Conference.

[60]  Heinrich Theodor Vierhaus,et al.  CMOS bridges and resistive transistor faults: IDDQ versus delay effects , 1993, Proceedings of IEEE International Test Conference - (ITC).

[61]  Jacob Savir,et al.  Random Pattern Testability of Delay Faults , 1988, IEEE Trans. Computers.

[62]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[63]  Edward J. McCluskey,et al.  "RESISTIVE SHORTS" WITHIN CMOS GATES , 1991, 1991, Proceedings. International Test Conference.

[64]  H.G. Kerkhoff,et al.  Scan cell design for enhanced delay fault testability , 1992, [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit.

[65]  T. Ghewala.  CrossCheck: A Cell Based VLSI Testability Solution , 1989, DAC.

[66]  Sudhakar M. Reddy,et al.  On the design of robust testable CMOS combinational logic circuits , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[67]  Kurt Keutzer,et al.  Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits , 1990, DAC '90.

[68]  Thomas W. Williams,et al.  A logic design structure for LSI testability , 1977, DAC '77.

[69]  K. Taniguchi,et al.  Time-dependent-dielectric breakdown of thin thermally grown SiO2films , 1985, IEEE Transactions on Electron Devices.

[70]  C. Hu,et al.  Reliability issues of MOS and bipolar ICs , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[71]  Edward J. McCluskey,et al.  Very-low-voltage testing for weak CMOS logic ICs , 1993, Proceedings of IEEE International Test Conference - (ITC).

[72]  Kurt Keutzer,et al.  A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits , 1991, 1991, Proceedings. International Test Conference.

[73]  Jacob Savir,et al.  Skewed-Load Transition Test: Part I, Calculus , 1992, Proceedings International Test Conference 1992.

[74]  Eric Lindbloom,et al.  Transition Fault Simulation , 1987, IEEE Design & Test of Computers.

[75]  Sudhakar M. Reddy,et al.  On the computation of the ranges of detected delay fault sizes , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[76]  Edward J. McCluskey,et al.  On-line delay testing of digital circuits , 1994, Proceedings of IEEE VLSI Test Symposium.

[77]  Gopalakrishnan Vijayan,et al.  Optimized test application timing for AC test , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[78]  Sudhakar M. Reddy,et al.  On the design of robust multiple fault testable CMOS combinational logic circuits , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[79]  M. Ray Mercer,et al.  Statistical delay fault coverage and defect level for delay faults , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[80]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[81]  Edward J. McCluskey,et al.  Logic design principles - with emphasis on testable semicustom circuits , 1986, Prentice Hall series in computer engineering.

[82]  Richard D. Eldred.  Test Routines Based on Symbolic Logical Statements , 1959, JACM.

[83]  Kaushik Roy,et al.  Synthesis of delay fault testable combinational logic , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[84]  Edward B. Eichelberger,et al.  Hazard Detection in Combinational and Sequential Switching Circuits , 1964, IBM J. Res. Dev..

[85]  Michael D. Ciletti,et al.  Arrangement of latches in scan-path design to improve delay fault coverage , 1990, Proceedings. International Test Conference 1990.

[86]  Barry K. Rosen,et al.  Delay test generation. II. Algebra and algorithms , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[87]  J. Max Cortner.  Digital Test Engineering , 1987 .

[88]  John E. Bauer,et al.  An Advanced Fault Isolation System for Digital Logic , 1975, IEEE Transactions on Computers.

[89]  Charles F. Hawkins,et al.  Quiescent power supply current measurement for CMOS IC defect detection , 1989 .

[90]  Andrew Lim,et al.  The role of long and short paths in circuit performance optimization , 1992, DAC '92.

[91]  Barry K. Rosen,et al.  Comparison of AC Self-Testing Procedures , 1983, ITC.

[92]  Edward J. McCluskey,et al.  Transients in combinational logic circuits , 1962 .