Symbolic Model Checking
暂无分享,去创建一个
Sérgio Vale Aguiar Campos | Edmund M. Clarke | Kenneth L. McMillan | Vasiliki Hartonas-Garmhausen | K. McMillan | S. Campos | Vasiliki Hartonas-Garmhausen | Edmund M. Clarke | Kenneth L. McMillan
[1] Sérgio Vale Aguiar Campos,et al. Computing quantitative characteristics of finite-state real-time systems , 1994, 1994 Proceedings Real-Time Systems Symposium.
[2] Randal E. Bryant,et al. Symbolic Boolean manipulation with ordered binary-decision diagrams , 1992, CSUR.
[3] Edmund M. Clarke,et al. Symbolic Model Checking: 10^20 States and Beyond , 1990, Inf. Comput..
[4] Edmund M. Clarke,et al. Verification Tools for Finite-State Concurrent Systems , 1993, REX School/Symposium.
[5] Somesh Jha,et al. Verification of the Futurebus+ cache coherence protocol , 1993, Formal Methods Syst. Des..
[6] Robert K. Brayton,et al. Implicit state enumeration of finite state machines using BDD's , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[7] Edmund M. Clarke,et al. Word level model checking—avoiding the Pentium FDIV error , 1996, DAC '96.
[8] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[9] Sérgio Vale Aguiar Campos,et al. Timing analysis of industrial real-time systems , 1995, Proceedings of 1995 IEEE Workshop on Industrial-Strength Formal Specification Techniques.
[10] Sérgio Vale Aguiar Campos,et al. Verifying the performance of the PCI local bus using symbolic techniques , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.
[11] Edmund M. Clarke,et al. Model checking and abstraction , 1994, TOPL.
[12] Edmund M. Clarke,et al. Deadlock prevention in flexible manufacturing systems using symbolic model checking , 1996, Proceedings of IEEE International Conference on Robotics and Automation.
[13] Edmund M. Clarke,et al. Automatic verification of industrial designs , 1995, Proceedings of 1995 IEEE Workshop on Industrial-Strength Formal Specification Techniques.
[14] Edmund M. Clarke,et al. Symbolic model checking for sequential circuit verification , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[15] Olivier Coudert,et al. Verifying Temporal Properties of Sequential Machines without Building Their State Diagrams , 1990, CAV.
[16] Somesh Jha,et al. Exploiting symmetry in temporal logic model checking , 1993, Formal Methods Syst. Des..