Layout Scaling of $\hbox{Si}_{1-x}\hbox{Ge}_{x} \hbox{-Channel}$ pFETs

Through a combination of electrical measurements, technology computer-aided design simulations, and wafer bending experiments, the effect of elastic stress relaxation on the layout dependence of Si1-xGex-channel p-channel field-effect transistors (pFETs) is studied. This work focuses on scaling of the transistor width W, the active-area length (length of diffusion, LOD) for isolated transistors, and poly-to-poly length LP/P of nested configurations. A strong narrow-width current enhancement is reported, even for relatively large widths, above 100 nm. On the other hand, the layout dependence on LOD or LP/P is also predicted but only for aggressively scaled layouts (LOD or LP/P below 100 nm). W and LP/P scaling lead to current enhancement, whereas LOD scaling is expected to degrade performance. No significant dependence of short-channel threshold voltage on W, LOD, or LP/P was observed. This study indicates that, as higher germanium concentrations of the channel lead to more layout dependence, this concentration may need to be optimized carefully to combine high channel mobility with limited added design complexity. Moreover, the channel thickness should be kept as thin as possible, as layout dependence is enhanced for thicker channels.

[1]  E. Bugiel,et al.  Raman investigations of elastic strain relief in Si1−xGex layers on patterned silicon substrate , 1993 .

[2]  G. Eneman,et al.  Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study , 2007, IEEE Transactions on Electron Devices.

[3]  E. Simoen,et al.  Gate Influence on the Layout Sensitivity of $ \hbox{Si}_{1 - x}\hbox{Ge}_{x}\ \hbox{S/D}$ and $\hbox{Si}_{1 - y}\hbox{C}_{y}\ \hbox{S/D}$ Transistors Including an Analytical Model , 2008, IEEE Transactions on Electron Devices.

[4]  Francois Andrieu,et al.  Elastic relaxation in patterned and implanted strained silicon on insulator , 2009 .

[5]  L. Witters,et al.  8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS , 2010, 2010 Symposium on VLSI Technology.

[6]  C. Ortolland,et al.  High-mobility Si1−xGex-channel PFETs: Layout dependence and enhanced scalability, demonstrating 90% performance boost at narrow widths , 2010, 2010 Symposium on VLSI Technology.

[7]  Wen-Kuan Yeh,et al.  The Geometry Effect of Contact Etch Stop Layer Impact on Device Performance and Reliability for 90-nm SOI nMOSFETs , 2006, IEEE Transactions on Electron Devices.

[8]  Yu Cao,et al.  Compact modeling of stress effects in scaled CMOS , 2009, 2009 International Conference on Simulation of Semiconductor Processes and Devices.

[9]  Y. Nishi,et al.  High quality GeO2/Ge interface formed by SPA radical oxidation and uniaxial stress engineering for high performance Ge NMOSFETs , 2006, 2009 Symposium on VLSI Technology.

[10]  X. Garros,et al.  20nm gate length trigate pFETs on strained SGOI for high performance CMOS , 2010, 2010 Symposium on VLSI Technology.

[11]  Manfred Horstmann,et al.  Detailed simulation study of embedded SiGe and Si:C source/drain stressors in nanoscaled silicon on insulator metal oxide semiconductor field effect transistors , 2010 .

[12]  T. Noguchi,et al.  Mobility improvement for 45nm node by combination of optimized stress and channel orientation design , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[13]  Hsing-Huang Tseng,et al.  Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme , 2007, 2007 IEEE Symposium on VLSI Technology.

[14]  R. Jammy,et al.  SiGe CMOS on (110) channel orientation with mobility boosters : Surface orientation, channel directions, and uniaxial strain , 2010, 2010 Symposium on VLSI Technology.

[15]  O. Weber,et al.  Examination of Additive Mobility Enhancements for Uniaxial Stress Combined with Biaxially Strained Si, Biaxially Strained SiGe and Ge Channel MOSFETs , 2007, 2007 IEEE International Electron Devices Meeting.